mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
synced 2025-05-19 16:02:36 +02:00
332 lines
7.3 KiB
Text
332 lines
7.3 KiB
Text
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/bcm963xx_dt_bindings.h>
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#define GIC_DIST_BASE 0x81001000
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#define GIC_CPUI_BASE 0x81002000
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#define TIMER_HYP_PPI 10
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#define TIMER_VIRT_PPI 11
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#define TIMER_PHYS_SECURE_PPI 13
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#define TIMER_PHYS_NONSECURE_PPI 14
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#define GIC_DIST_BASE 0x81001000
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#define GIC_CPUI_BASE 0x81002000
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#define PMU_CORE0_SPI 7
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#define PMU_CORE1_SPI 8
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#define PMU_CORE2_SPI 9
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#define PMU_CORE3_SPI 10
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#define SDIO_EMMC_SPI 86
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#define SPU_GMAC_SPI 91
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#define ARM_UART0_SPI 32
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/dts-v1/;
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/* For secondary boot area */
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/memreserve/ 0x00000000 0x00008000;
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/* For PMC3 firmware */
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#define DEVICE_TREE
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#include "../../../shared/opensource/include/pmc/pmc_firmware_63178.h"
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/memreserve/ PMC3_RESERVED_MEM_START PMC3_RESERVED_MEM_SIZE;
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#undef DEVICE_TREE
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#include "../bcm_963xx_template.dtsi"
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#include "../bcm_rsvdmem_32.dtsi"
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/ {
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model = "Broadcom BCM963178";
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compatible = "brcm,bcm963178";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "console=ttyAMA0 earlyprintk debug irqaffinity=0 pci=pcie_bus_safe";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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CA7_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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};
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CA7_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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#if defined (CONFIG_OPTEE)
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enable-method = "psci";
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#else
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enable-method = "brcm,bca-smp";
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#endif
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};
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CA7_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x2>;
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next-level-cache = <&L2_0>;
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#if defined (CONFIG_OPTEE)
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enable-method = "psci";
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#else
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enable-method = "brcm,bca-smp";
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#endif
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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#if defined (CONFIG_OPTEE)
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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cpu_off = <1>;
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cpu_on = <2>;
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};
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firmware {
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optee {
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compatible = "linaro,optee-tz";
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method = "smc";
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};
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};
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#endif
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gic: interrupt-controller@81000000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <GIC_DIST_BASE 0x1000>,
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<GIC_CPUI_BASE 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI TIMER_PHYS_SECURE_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI TIMER_PHYS_NONSECURE_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI TIMER_VIRT_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI TIMER_HYP_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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arm,cpu-registers-not-fw-configured = <1>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI PMU_CORE0_SPI IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI PMU_CORE1_SPI IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CA7_0>,
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<&CA7_1>;
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};
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uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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i2s_clkmclk_syscon: i2s_clkmclk_syscon{
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compatible = "brcm,i2s-audio-clkmclk-syscon", "syscon";
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reg = <0xFF802080 0x4>;
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};
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osc: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <200000000>; /* xpon 200MHz output */
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};
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i2sclk: i2sclk {
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#clock-cells = <0>;
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compatible = "brcm,i2s-clock";
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clocks = <&osc>;
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clk-mclk-syscon = <&i2s_clkmclk_syscon>;
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clock-output-names = "i2s_clk";
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};
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};
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/* Legacy UBUS base */
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ubus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xff800000 0x7fffff>;
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nand@ff801800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm63xx", "brcm,brcmnand-v7.1";
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reg = <0x1800 0x600>, <0x2000 0x10>;
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reg-names = "nand", "nand-int-base";
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status = "okay";
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nandcs@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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nand-on-flash-bbt;
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};
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};
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watchdog@480 {
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compatible = "brcm,bcm96xxx-wdt";
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reg = <0x480 0x10>;
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timeout-sec = <80>;
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};
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gpio7: gpio-controller@0xff80051c {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x51c 0x4>, <0x53c 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio6: gpio-controller@0xff800518 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x518 0x4>, <0x538 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio5: gpio-controller@0xff800514 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x514 0x4>, <0x534 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio4: gpio-controller@0xff800510 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x510 0x4>, <0x530 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio3: gpio-controller@0xff80050c {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x50c 0x4>, <0x52c 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio2: gpio-controller@0xff800508 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x508 0x4>, <0x528 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio1: gpio-controller@0xff800504 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x504 0x4>, <0x0 0x524 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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gpio0: gpio-controller@0xff800500 {
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compatible = "brcm,bcm6345-gpio";
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reg-names = "dirout", "dat";
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reg = <0x500 0x4>, <0x520 0x4>;
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ngpios = <32>;
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#gpio-cells = <2>;
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gpio-controller;
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};
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i2s: bcm63xx-i2s {
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compatible = "brcm,bcm63xx-i2s";
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reg = <0x2080 0x21>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2sclk>, <&osc>;
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clock-names = "i2sclk","i2sosc";
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};
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serial@ff812000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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interrupts = <GIC_SPI ARM_UART0_SPI IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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};
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brcm-legacy {
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compatible = "brcm,brcm-legacy";
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};
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cs4345 {
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compatible = "crus,cs4345-dac";
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};
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#if defined(CONFIG_BCM_PCIE_HCD)
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pcie1: pcie@84000000 {
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compatible = "brcm,bcm963xx-vpcie";
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device_type = "vpci";
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reg = <0x84000000 0x01000000>;
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brcm,coreid = <1>;
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};
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pcie0: pcie@80040000 {
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compatible = "brcm,bcm963xx-pcie";
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device_type = "pci";
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reg = <0x80040000 0x0000A000>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* flags, pci_addr, cpu_addr, size */
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ranges = <0x02000000 0 0xC0000000 0xC0000000 0 0x10000000>;
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interrupt-names = "intr";
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interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; /* core error log interrupts */
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
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brcm,coreid = <0>;
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};
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#endif
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therm0: brcm-therm {
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compatible = "brcm,therm";
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status = "okay";
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};
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};
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