mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
synced 2025-05-19 16:02:36 +02:00
167 lines
4 KiB
Text
167 lines
4 KiB
Text
#define GIC_DIST_BASE 0x81001000
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#define GIC_CPUI_BASE 0x81002000
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#define TIMER_HYP_PPI 10
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#define TIMER_VIRT_PPI 11
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#define TIMER_PHYS_SECURE_PPI 13
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#define TIMER_PHYS_NONSECURE_PPI 14
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#define PMU_CORE0_SPI 9
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#define PMU_CORE1_SPI 10
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#define PMU_CORE2_SPI 11
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#define PMU_CORE3_SPI 12
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#define HS_SPIM_SPI 37
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#define SDIO_EMMC_SPI 95
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#define SPU_GMAC_SPI 118
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#include "../bcm_b53_template.dtsi"
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#include "../bcm_rsvdmem_64.dtsi"
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/ {
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aliases {
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spi1 = &hsspi; /* 0 = legacy, 1 = high speed */
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};
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/* this is actually the PLL but we have no clock framework */
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hsspi_pll: hsspi-pll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <400000000>;
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};
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/* Legacy UBUS base */
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ubus@ff800000 {
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nand@ff801800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm63xx", "brcm,brcmnand-v7.1";
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reg = <0x0 0x1800 0x0 0x600>, <0x0 0x2000 0x0 0x10>;
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reg-names = "nand", "nand-int-base";
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status = "okay";
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nandcs@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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nand-on-flash-bbt;
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};
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};
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watchdog@ff802780 {
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compatible = "brcm,bcm96xxx-wdt";
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reg = <0x0 0x2780 0x0 0x10>;
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timeout-sec = <80>;
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};
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/* 6858 use second i2c bus for pon sfp i2c device */
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i2c_0: i2c@ff85a800 {
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compatible = "brcm,bcm63000-i2c";
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reg = <0x0 0x5a800 0x0 0x60>;
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};
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/* not enabling the first i2c bus until pon sfp driver fix
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the assumption that only one i2c bus in the system
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i2c_1: i2c@ff802100 {
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compatible = "brcm,bcm63000-i2c";
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reg = <0x0 0x2100 0x0 0x60>;
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};*/
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hsspi: spi@0xff801000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,bcm6328-hsspi";
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reg = <0x0 0x1000 0x0 0x600>;
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clocks = <&hsspi_pll>, <&hsspi_pll>;
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clock-names = "hsspi", "pll";
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spi-max-frequency = <100000000>;
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num-cs = <8>;
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cs-gpios = <0>, <0>;
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interrupts = <GIC_SPI HS_SPIM_SPI IRQ_TYPE_LEVEL_HIGH>;
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status = "okay";
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};
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};
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pdc0: spu-pdc@0x8001c000 {
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compatible = "brcm,pdc";
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reg = <0x00000000 0x8001c000 0x00000000 0x448>;
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interrupts = <GIC_SPI SPU_GMAC_SPI IRQ_TYPE_LEVEL_HIGH>;
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brcm,num_chan = <1>;
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};
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spu-crypto@0x8001d000 {
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compatible = "brcm,spu-crypto";
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reg = <0x00000000 0x8001d000 0x00000000 0x64>;
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brcm,num_spu = <1>;
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};
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#if defined(CONFIG_BCM_PCIE_HCD)
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pcie0: pcie@80040000 {
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compatible = "brcm,bcm963xx-pcie";
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device_type = "pci";
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reg = <0 0x80040000 0 0x0000A000>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* flags, pci_addr, cpu_addr size */
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ranges = <0x02000000 0 0xC0000000 0 0xC0000000 0 0x10000000>;
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/* core error log interrupts */
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interrupt-names = "intr";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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brcm,coreid = <0>;
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};
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pcie1: pcie@80050000 {
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compatible = "brcm,bcm963xx-pcie";
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device_type = "pci";
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reg = <0 0x80050000 0 0x0000A000>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* flags, pci_addr, cpu_addr size */
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ranges = <0x02000000 0 0xD0000000 0 0xD0000000 0 0x10000000>;
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/* core error log interrupts */
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interrupt-names = "intr";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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brcm,coreid = <1>;
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};
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pcie2: pcie@80060000 {
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compatible = "brcm,bcm963xx-pcie";
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device_type = "pci";
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reg = <0 0x80060000 0 0x0000A000>;
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#address-cells = <3>;
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#size-cells = <2>;
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/* flags, pci_addr, cpu_addr size */
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ranges = <0x02000000 0 0xE0000000 0 0xE0000000 0 0x10000000>;
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/* core error log interrupts */
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interrupt-names = "intr";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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brcm,coreid = <2>;
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};
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#endif
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therm0: brcm-therm {
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compatible = "brcm,therm";
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reboot-temperature = <130000>; /* millicelsius */
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status = "okay";
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};
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};
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