mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
synced 2025-05-19 16:02:36 +02:00
137 lines
3.2 KiB
Text
137 lines
3.2 KiB
Text
#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/soc/bcm963xx_dt_bindings.h>
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#define GIC_DIST_BASE 0x81001000
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#define GIC_CPUI_BASE 0x81002000
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#define TIMER_HYP_PPI 10
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#define TIMER_VIRT_PPI 11
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#define TIMER_PHYS_SECURE_PPI 13
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#define TIMER_PHYS_NONSECURE_PPI 14
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#define PMU_CORE0_SPI 9
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#define PMU_CORE1_SPI 10
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#define ARM_UART0_SPI 92
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/dts-v1/;
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/ {
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model = "Broadcom BCM96878";
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compatible = "brcm,bcm96878";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen {
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bootargs = "console=ttyAMA0 earlyprintk mem=64M,1048576 debug root=/dev/ram0 ro";
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linux,initrd-start = <0x1b00000>;
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linux,initrd-end = <0x1fff000>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "brcm,bca-smp";
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CA7_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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next-level-cache = <&L2_0>;
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};
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CA7_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x1>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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gic: interrupt-controller@81000000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <GIC_DIST_BASE 0x1000>,
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<GIC_CPUI_BASE 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI TIMER_PHYS_SECURE_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI TIMER_PHYS_NONSECURE_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI TIMER_VIRT_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI TIMER_HYP_PPI (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupts = <GIC_SPI PMU_CORE0_SPI IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI PMU_CORE1_SPI IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&CA7_0>,
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<&CA7_1>;
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};
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brcm-legacy {
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compatible = "brcm,brcm-legacy";
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};
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memory@00000000 {
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device_type = "memory";
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reg = <0x00000000 0x04000000>; /* 64MBMB */
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};
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uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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};
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/* Legacy UBUS base */
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ubus@ff800000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xff800000 0x7fffff>;
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nand@ff801800 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "brcm,nand-bcm63xx", "brcm,brcmnand-v7.1";
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reg = <0x2000 0x600>, <0x2000 0x10>;
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reg-names = "nand", "nand-int-base";
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status = "okay";
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nandcs@0 {
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compatible = "brcm,nandcs";
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reg = <0>;
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nand-on-flash-bbt;
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};
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};
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watchdog@480 {
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compatible = "brcm,bcm96xxx-wdt";
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reg = <0x480 0x10>;
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timeout-sec = <80>;
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};
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serial@ff812000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x12000 0x1000>;
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interrupts = <GIC_SPI ARM_UART0_SPI IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&uartclk>, <&uartclk>;
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clock-names = "uartclk", "apb_pclk";
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};
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};
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};
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