mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
synced 2025-05-19 07:51:46 +02:00
130 lines
6.2 KiB
C
130 lines
6.2 KiB
C
#include "bp_defs.h"
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#include "boardparms.h"
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#include "bcmSpiRes.h"
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extern BpCmdElem moca6802InitSeq[];
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static bp_elem_t g_bcm947189ref[] = {
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/* Unmanaged switch in RGMII 0 */
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{bp_cpBoardId, .u.cp = "947189REF"},
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{bp_ucPhyType0, .u.uc = BP_ENET_NO_PHY},
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{bp_ulPortMap, .u.ul = 0x1},
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{bp_ucPhyAddress, .u.uc = 0x1e},
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/* Only one port definition: unmanaged switch */
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{bp_ulPhyId0, .u.ul = 0x1e | MAC_IF_RGMII},
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{bp_usPhyConnType, .u.us = PHY_CONN_TYPE_EXT_SW},
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{bp_ucPhyDevName, .u.cp = "eth0"},
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{bp_usGpioPhyReset, .u.us = 0x02},
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/* Need to set TRFC_160NS for 2Gb DDR chip */
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/* {bp_ulMemoryConfig, .u.ul = BP_DDR_DEVICE_WIDTH_16 | BP_DDR_TRFC_160NS}, */
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{bp_last}
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};
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static bp_elem_t g_bcm947189ref2[] = {
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/* GPHY in RGMII 0, PLC in RGMII 1 */
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{bp_cpBoardId, .u.cp = "947189REF2"},
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{bp_ucPhyType0, .u.uc = BP_ENET_NO_PHY},
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{bp_ulPortMap, .u.ul = 0x3},
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{bp_ulPhyId0, .u.ul = 25 | MAC_IF_RGMII},
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{bp_usPhyConnType, .u.us = PHY_CONN_TYPE_EXT_PHY},
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{bp_ucPhyDevName, .u.cp = "eth0"},
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{bp_usGpioPhyReset, .u.us = 0x02},
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{bp_ulPhyId1, .u.ul = BP_PHY_ID_2 | MAC_IF_RGMII},
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{bp_usPhyConnType, .u.us = PHY_CONN_TYPE_PLC},
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{bp_ucPhyDevName, .u.cp = "plc0"},
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{bp_last}
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};
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static bp_elem_t g_bcm947189acnrm[] = {
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/* managed switch in RGMII 0 */
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{bp_cpBoardId, .u.cp = "947189acnrm"},
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{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_7_AL },
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{bp_usExtIntrSesBtnWireless, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_9_AL},
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{bp_usGpioLedSesWireless, .u.us = BP_GPIO_10_AH},
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{bp_ucPhyType0, .u.uc = BP_ENET_NO_PHY},
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{bp_ulPortMap, .u.ul = 0x1},
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{bp_ucPhyAddress, .u.uc = 0x0},
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/* Only one port definition: managed switch */
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{bp_ulPhyId0, .u.ul = RGMII_DIRECT | EXTSW_CONNECTED},
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{bp_usGpioPhyReset, .u.us = 0x02},
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{bp_ucPhyType1, .u.uc = BP_ENET_EXTERNAL_SWITCH},
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{bp_ucPhyAddress, .u.uc = 0x0},
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{bp_usConfigType, .u.us = BP_ENET_CONFIG_MDIO},
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{bp_ucPhyAddress, .u.uc = 0x0},
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{bp_ulPortMap, .u.ul = 0x1f},
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{bp_ulPhyId0, .u.ul = 0x00 | CONNECTED_TO_EXTERN_SW},
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{bp_ulPhyId1, .u.ul = 0x01 | CONNECTED_TO_EXTERN_SW},
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{bp_ulPhyId2, .u.ul = 0x02 | CONNECTED_TO_EXTERN_SW},
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{bp_ulPhyId3, .u.ul = 0x03 | CONNECTED_TO_EXTERN_SW},
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{bp_ulPhyId4, .u.ul = 0x04 | CONNECTED_TO_EXTERN_SW},
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{bp_usUsbPwrOn0, .u.us = BP_GPIO_8_AL},
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{bp_ulMemoryConfig, .u.ul = BP_DDR_DEVICE_WIDTH_16 | BP_DDR_TOTAL_WIDTH_32BIT},
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{bp_last}
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};
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static bp_elem_t g_bcm947189acnrh[] = {
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/* managed switch in RGMII 0 */
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{bp_cpBoardId, .u.cp = "947189acnrh"},
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{bp_elemTemplate, .u.bp_elemp = g_bcm947189acnrm},
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{bp_last}
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};
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static bp_elem_t g_bcm947189acdbmr[] = {
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{bp_cpBoardId, .u.cp = "947189acdbmr"},
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{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_7_AL },
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{bp_usExtIntrSesBtnWireless, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_9_AL},
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{bp_usGpioMocaReset, .u.us = BP_GPIO_2_AH},
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{bp_usGpioSpiClk, .u.us = BP_GPIO_21_AH},
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{bp_usGpioSpiCs, .u.us = BP_GPIO_24_AH},
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{bp_usGpioSpiMiso, .u.us = BP_GPIO_22_AH},
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{bp_usGpioSpiMosi, .u.us = BP_GPIO_23_AH},
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{bp_usGpioLedSesWireless, .u.us = BP_GPIO_10_AH},
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{bp_ucPhyType0, .u.uc = BP_ENET_NO_PHY},
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{bp_ulPortMap, .u.ul = 0x1},
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{bp_ucPhyAddress, .u.uc = 0x0},
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{bp_ulPhyId0, .u.ul = 10 | MAC_IF_RGMII | PHY_INTEGRATED_VALID | PHY_EXTERNAL},
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{bp_usPhyConnType, .u.us = PHY_CONN_TYPE_MOCA_ETH},
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{bp_usUsbPwrOn0, .u.us = BP_GPIO_8_AL},
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{bp_last}
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};
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static bp_elem_t g_bcm947452eapl[] = {
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{bp_cpBoardId, .u.cp = "947452eapl"},
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{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_7_AL },
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{bp_usExtIntrSesBtnWireless, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_9_AL},
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{bp_usGpioLedSesWireless, .u.us = BP_GPIO_10_AH},
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{bp_ucPhyType0, .u.uc = BP_ENET_NO_PHY},
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{bp_ulPortMap, .u.ul = 0x1},
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{bp_ulPhyId0, .u.ul = 25 | MAC_IF_RGMII | PHY_INTEGRATED_VALID | PHY_EXTERNAL | (ADVERTISE_ALL_GMII | PHY_ADV_CFG_VALID)},
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{bp_usPhyConnType, .u.us = PHY_CONN_TYPE_EXT_PHY},
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{bp_ucPhyDevName, .u.cp = "eth0"},
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{bp_usGpioPhyReset, .u.us = 0x02},
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{bp_last}
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};
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static bp_elem_t g_bcm947189acr[] = {
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{bp_cpBoardId, .u.cp = "947189acr"},
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{bp_usExtIntrResetToDefault, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_4_AL },
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{bp_usExtIntrSesBtnWireless, .u.us = BP_EXT_INTR_SHARED | BP_EXT_INTR_TYPE_IRQ_LOW_LEVEL | BP_EXT_INTR_0},
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{bp_usGpio_Intr, .u.us = BP_GPIO_5_AL},
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{bp_usGpioLedSesWireless, .u.us = BP_GPIO_7_AH},
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{bp_ucPhyType0, .u.uc = BP_ENET_NO_PHY},
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{bp_ulPortMap, .u.ul = 0x1},
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{bp_ulPhyId0, .u.ul = 24 | MAC_IF_RGMII | PHY_INTEGRATED_VALID | PHY_EXTERNAL | (ADVERTISE_ALL_GMII | PHY_ADV_CFG_VALID)},
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{bp_usPhyConnType, .u.us = PHY_CONN_TYPE_EXT_PHY},
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{bp_ucPhyDevName, .u.cp = "eth0"},
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{bp_usGpioPhyReset, .u.us = 0x09},
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{bp_usUsbPwrOn0, .u.us = BP_GPIO_2_AL},
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{bp_last}
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};
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bp_elem_t * g_BoardParms[] = {g_bcm947189ref, g_bcm947189ref2, g_bcm947189acnrm, g_bcm947189acnrh, g_bcm947189acdbmr, g_bcm947452eapl, g_bcm947189acr, 0};
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