mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
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280 lines
8.2 KiB
C
280 lines
8.2 KiB
C
/*
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<:copyright-BRCM:2013:DUAL/GPL:standard
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Copyright (c) 2013 Broadcom
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All Rights Reserved
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Unless you and Broadcom execute a separate written software license
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agreement governing use of this software, this software is licensed
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to you under the terms of the GNU General Public License version 2
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(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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with the following added to such license:
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As a special exception, the copyright holders of this software give
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you permission to link this software with independent modules, and
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to copy and distribute the resulting executable under terms of your
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choice, provided that you also meet, for each linked independent
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module, the terms and conditions of the license of that module.
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An independent module is a module which is not derived from this
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software. The special exception does not apply to any modifications
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of the software.
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Not withstanding the above, under no circumstances may you combine
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this software in any way with any other Broadcom software provided
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under a license other than the GPL, without Broadcom's express prior
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written consent.
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:>
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*/
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#ifndef _CFE_
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#endif
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#include <boardparms.h>
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#include "pmc_drv.h"
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#include "pmc_pcie.h"
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#include "BPCM.h"
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#include "bcm_ubus4.h"
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#include "bcm_map_part.h"
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static const int pmc_pcie_pmb_addr[]= {
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#if defined(CONFIG_BCM963138) || defined(CONFIG_BCM963148) || defined(CONFIG_BCM96846) || defined(CONFIG_BCM96855)
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PMB_ADDR_PCIE0,
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PMB_ADDR_PCIE1
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#elif defined(CONFIG_BCM94908) || defined(CONFIG_BCM96856)
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PMB_ADDR_PCIE0,
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PMB_ADDR_PCIE1,
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PMB_ADDR_PCIE2
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#elif defined(CONFIG_BCM963158)
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PMB_ADDR_PCIE0,
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PMB_ADDR_PCIE1,
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PMB_ADDR_PCIE2,
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PMB_ADDR_PCIE3,
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#elif defined(CONFIG_BCM96858)
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PMB_ADDR_PCIE0,
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PMB_ADDR_PCIE1,
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PMB_ADDR_PCIE_UBUS
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#else /* CONFIG_BCM963381, CONFIG_BCM96848, CONFIG_BCM963178, CONFIG_BCM947622 CONFIG_BCM96878 */
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PMB_ADDR_PCIE0
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#endif
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};
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#define MAX_PCIE_UNIT (sizeof(pmc_pcie_pmb_addr)/sizeof(int))
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#if defined (CONFIG_BCM96858) || defined(CONFIG_BCM96856)
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/* registration/deregistration is automatic enable if needed */
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//#define UBUS_NODE_REGISTRATION 1
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#endif
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#define PCIE_INVALID_PORT 0
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#define PCIE_STANDALONE_PORT 1
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#define PCIE_BIFURCATED_PORT 2
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typedef struct {
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int port_type;
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int slv_node;
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int mst_node;
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} ubus_node_info_t;
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/* PCIe port UBUS */
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static const ubus_node_info_t pmc_pcie_ubus_node[] = {
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#if defined (CONFIG_BCM96858)
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{PCIE_BIFURCATED_PORT, UCB_NODE_ID_SLV_PCIE0, UCB_NODE_ID_MST_PCIE0},
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{PCIE_BIFURCATED_PORT, UCB_NODE_ID_SLV_PCIE0, UCB_NODE_ID_MST_PCIE0},
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{PCIE_STANDALONE_PORT, UCB_NODE_ID_SLV_PCIE2, UCB_NODE_ID_MST_PCIE2}
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#elif defined(CONFIG_BCM96856)
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{PCIE_BIFURCATED_PORT, UCB_NODE_ID_SLV_PCIE0, UCB_NODE_ID_MST_PCIE0},
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{PCIE_BIFURCATED_PORT, UCB_NODE_ID_SLV_PCIE0, UCB_NODE_ID_MST_PCIE0}
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#elif defined(CONFIG_BCM96846)
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{PCIE_BIFURCATED_PORT, UCB_NODE_ID_SLV_PCIE0, UCB_NODE_ID_MST_PCIE0},
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{PCIE_BIFURCATED_PORT, UCB_NODE_ID_SLV_PCIE0, UCB_NODE_ID_MST_PCIE0}
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#else
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/* SoC that does not require UBUS registration */
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{PCIE_INVALID_PORT, -1, -1},
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{PCIE_INVALID_PORT, -1, -1},
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{PCIE_INVALID_PORT, -1, -1},
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{PCIE_INVALID_PORT, -1, -1}
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#endif
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};
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void pmc_pcie_register_ubus(int unit)
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{
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/* Skip registration for ubus earlier than UBUS4 */
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if (pmc_pcie_ubus_node[unit].port_type == PCIE_INVALID_PORT) {
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return;
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}
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#if defined(UBUS_NODE_REGISTRATION)
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/* Register slave node */
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ubus_register_port(pmc_pcie_ubus_node[unit].slv_node);
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/* Register master node */
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ubus_register_port(pmc_pcie_ubus_node[unit].mst_node);
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#endif /* UBUS_NODE_REGISTRATION */
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return;
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}
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void pmc_pcie_deregister_ubus(int unit)
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{
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/* Skip deregistration for ubus earlier than UBUS4 */
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/* skip deregister for bifurcated ports */
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if (pmc_pcie_ubus_node[unit].port_type != PCIE_STANDALONE_PORT) {
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return;
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}
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#if defined(UBUS_NODE_REGISTRATION)
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/* unegister slave node */
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ubus_deregister_port(pmc_pcie_ubus_node[unit].slv_node);
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/* Unegister master node */
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ubus_deregister_port(pmc_pcie_ubus_node[unit].mst_node);
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#endif /* UBUS_NODE_REGISTRATION */
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return;
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}
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/**
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* Re-configure UBUS4 for the given PCI-E core.
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* - master token credits for PCIE -> Runner access
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* - master decode window
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*/
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static void pmc_pcie_ubus_init(int unit)
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{
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#if defined(CONFIG_BCM96858)
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int unit2mst_node_tbl[] = {UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_PCIE2};
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/* These credits of PCIe to Runner quads are requiered to Wakeup runner
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* in case of DHD Offload RxComplete */
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apply_ubus_credit_each_master(unit2mst_node_tbl[unit]);
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#elif defined(CONFIG_BCM96846)
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/*In 6846 both PCIe shares the same UBUS Master*/
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int unit2mst_node_tbl[] = {UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_PCIE0};
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ubus_master_set_token_credits(unit2mst_node_tbl[unit], 9, 1);
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#elif defined(CONFIG_BCM963158)
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/*In 63158 PCIe#0,1 are bifurcated ports and shares the same UBUS Master */
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int unit2mst_node_tbl[] = {UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_PCIE2, UBUS_PORT_ID_PCIE3};
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apply_ubus_credit_each_master(unit2mst_node_tbl[unit]);
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#elif defined(CONFIG_BCM96856)
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int unit2mst_node_tbl[] = {UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_PCIE0, UBUS_PORT_ID_PCIE2};
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/* These credits of PCIe to Runner quads are requiered to Wakeup runner
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* in case of DHD Offload RxComplete */
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ubus_master_set_token_credits(unit2mst_node_tbl[unit], 9, 1);
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#elif defined(CONFIG_BCM963178) || defined(CONFIG_BCM947622) || defined(CONFIG_BCM96855)
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int unit2mst_node_tbl[] = {UBUS_PORT_ID_PCIE0};
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#endif
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#if defined(CONFIG_BCM_UBUS4_DCM)
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ubus_cong_threshold_wr(unit2mst_node_tbl[unit], 0);
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#endif
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#if defined(CONFIG_BCM_UBUS_DECODE_REMAP)
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ubus_master_remap_port(unit2mst_node_tbl[unit]);
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#endif
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}
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void pmc_pcie_power_up(int unit)
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{
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BPCM_SR_CONTROL sr_ctrl = {
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.Bits.sr = 0, // Only iddq
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};
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int addr, dual_lane;
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if (unit >= MAX_PCIE_UNIT)
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BUG_ON(1);
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addr = pmc_pcie_pmb_addr[unit];
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if (PowerOnZone(addr, 0))
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BUG_ON(1);
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mdelay(10);
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pmc_pcie_register_ubus(unit);
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if ((BpGetPciPortDualLane(unit, &dual_lane) == BP_SUCCESS) && dual_lane) {
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#if defined(CONFIG_BCM963158)
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int bifur_addr;
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/* Power up the other bi-furcated port */
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bifur_addr = pmc_pcie_pmb_addr[unit+1];
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if (PowerOnZone(bifur_addr, 0))
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BUG_ON(1);
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mdelay(10);
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if (WriteBPCMRegister(bifur_addr, BPCMRegOffset(sr_control), sr_ctrl.Reg32))
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BUG_ON(1);
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#endif
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sr_ctrl.Reg32 = 0x80; /* bit7: 1 - Strap override for dual lane support */
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/* bit6: Strap value, 0 - dual lane, 1 - single lane */
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/* reset */
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if (WriteBPCMRegister(addr, BPCMRegOffset(sr_control), 0xff))
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BUG_ON(1);
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mdelay(10);
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}
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if (WriteBPCMRegister(addr, BPCMRegOffset(sr_control), sr_ctrl.Reg32))
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BUG_ON(1);
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pmc_pcie_ubus_init(unit);
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}
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static void do_power_down(int addr, uint32 sr_ctrl)
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{
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if (WriteBPCMRegister(addr, BPCMRegOffset(sr_control), sr_ctrl))
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BUG_ON(1);
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mdelay(10);
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if (PowerOffZone(addr, 0))
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BUG_ON(1);
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}
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void pmc_pcie_power_down(int unit)
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{
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BPCM_SR_CONTROL sr_ctrl = {
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.Bits.sr = 4, // Only iddq
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};
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int addr;
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if (unit >= MAX_PCIE_UNIT)
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BUG_ON(1);
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addr = pmc_pcie_pmb_addr[unit];
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#if defined(CONFIG_BCM96858) || defined(CONFIG_BCM96856) || defined(CONFIG_BCM96846)
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/*On Bifurcation mode we must not shut down and de-register the ubus port of
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* bifurcated port (0) since we don't know the future status of core 1 */
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if (pmc_pcie_ubus_node[unit].port_type == PCIE_BIFURCATED_PORT)
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return;
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#endif
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#if defined(CONFIG_BCM963158)
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// To power down PLL and PLL-LDO for PCIe gen 3
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if (addr == PMB_ADDR_PCIE3) {
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sr_ctrl.Reg32 |= 1 << 29 | 1 << 30;
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}
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#endif
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#if defined(CONFIG_BCM963158) || defined(CONFIG_BCM96855)
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{
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int dual_lane, bifur_addr;
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/* Power down the other bi-furcated port if this supports dual lane */
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if ((BpGetPciPortDualLane(unit, &dual_lane) == BP_SUCCESS) && dual_lane) {
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/* Identify other bifurcated port address */
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bifur_addr = pmc_pcie_pmb_addr[unit+1];
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do_power_down(bifur_addr, sr_ctrl.Reg32);
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}
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}
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#endif
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do_power_down(addr, sr_ctrl.Reg32);
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pmc_pcie_deregister_ubus(unit);
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}
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#ifndef _CFE_
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EXPORT_SYMBOL(pmc_pcie_power_up);
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EXPORT_SYMBOL(pmc_pcie_power_down);
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#endif
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