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https://github.com/gnuton/asuswrt-merlin.ng.git
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217 lines
5.5 KiB
C
217 lines
5.5 KiB
C
#ifndef BPCM_H
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#define BPCM_H
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#include "bcmtypes.h"
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#ifndef NULL
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#define NULL ((void *)0)
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#endif
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typedef union
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{
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struct {
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uint32 sw_strap : 16;
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uint32 hw_rev : 8;
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uint32 pmb_Addr : 8;
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} Bits;
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uint32 Reg32;
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} BPCM_ID_REG;
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// types of PMB devices
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enum {
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kPMB_BPCM = 0,
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kPMB_MIPS_PLL = 1,
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kPMB_GEN_PLL = 2,
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kPMB_LC_PLL = 3,
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// 4..15 reserved
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};
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typedef union
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{
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struct {
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uint32 reserved1: 12;
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uint32 devType : 4; // see enum above
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uint32 reserved2: 8;
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uint32 num_zones: 8;
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} Bits;
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uint32 Reg32;
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} BPCM_CAPABILITES_REG;
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typedef union
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{
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struct {
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uint32 reserved : 31;
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uint32 pwd_alert: 1;
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} Bits;
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uint32 Reg32;
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} BPCM_STATUS_REG;
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typedef union
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{
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struct {
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uint32 interval : 16;
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uint32 alert_h : 1;
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uint32 valid_h : 1;
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uint32 alert_s : 1;
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uint32 valid_s : 1;
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uint32 reserved : 4;
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uint32 continuous_h : 1;
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uint32 continuous_s : 1;
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uint32 thresh_en_h : 1;
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uint32 thresh_en_s : 1;
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uint32 ectr_en_h : 1;
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uint32 ectr_en_s : 1;
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uint32 ro_en_h : 1;
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uint32 ro_en_s : 1;
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} Bits;
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uint32 Reg32;
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} BPCM_AVS_ROSC_CONTROL_REG;
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typedef union
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{
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struct {
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uint32 thresh_hi : 16;
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uint32 thresh_lo : 16;
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} Bits;
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uint32 Reg32;
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} BPCM_AVS_ROSC_THRESHOLD;
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typedef union
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{
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struct {
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uint32 count_h : 16;
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uint32 count_s : 16;
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} Bits;
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uint32 Reg32;
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} BPCM_AVS_ROSC_COUNT;
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typedef union
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{
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struct {
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uint32 reserved1 : 2;
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uint32 clr_cfg : 3;
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uint32 rsel : 3;
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uint32 ccfg : 8;
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uint32 alert : 1;
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uint32 reserved2 : 6;
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uint32 pwd_tm_en : 1;
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uint32 start : 6;
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uint32 pwd_alert_sel : 1;
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uint32 pwd_en : 1;
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} Bits;
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uint32 Reg32;
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} BPCM_AVS_PWD_CONTROL;
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typedef union
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{
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struct {
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uint32 reset_state : 1; // R/O
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uint32 iso_state : 1; // R/O
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uint32 mem_pwr_state : 1; // R/O
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uint32 dpg_pwr_state : 1; // R/O
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uint32 pwr_good : 1; // R/O
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uint32 pwr_on_state : 1; // R/O
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uint32 pwr_off_state : 1; // R/O
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uint32 freq_scalar_dyn_sel : 1; // R/O
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uint32 reserved : 11;
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uint32 blk_reset_assert : 1;
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uint32 mem_pwr_ctl_en : 1;
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uint32 pwr_up_req : 1;
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uint32 pwr_dn_req : 1;
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uint32 dpg_ctl_en : 1;
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uint32 manual_ctl : 1;
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uint32 manual_iso_ctl : 1;
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uint32 manual_mem_pwr : 2;
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uint32 dpg_capable : 1; // R/O
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uint32 freq_scale_used : 1; // R/O
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uint32 manual_reset_ctl : 1;
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uint32 manual_clk_en : 1;
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} Bits;
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uint32 Reg32;
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} BPCM_PWR_ZONE_N_CONTROL;
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typedef union
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{
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struct {
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uint32 reset_off_delay : 4;
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uint32 reset_on_delay : 4;
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uint32 clock_off_delay : 4;
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uint32 clock_on_delay : 4;
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uint32 iso_off_delay : 4;
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uint32 iso_on_delay : 4;
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uint32 reserved : 3;
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uint32 pwk_ok_thresh : 2;
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uint32 pwr_ok_delay_sel : 3;
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} Bits;
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uint32 Reg32;
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} BPCM_PWR_ZONE_N_CONFIG1;
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typedef union
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{
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struct {
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uint32 mem_off_delay : 4;
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uint32 mem_on_delay : 4;
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uint32 dpg_off_delay : 4;
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uint32 dpg1_on_delay : 4;
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uint32 dpg2_on_delay : 4;
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uint32 dpgn_on_delay : 4;
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uint32 reserved : 6;
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uint32 slew_prescale_sel : 3;
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uint32 delay_prescale_sel : 3;
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} Bits;
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uint32 Reg32;
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} BPCM_PWR_ZONE_N_CONFIG2;
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typedef union
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{
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struct {
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uint32 reserved : 22;
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uint32 high_gear_div : 3;
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uint32 low_gear_div : 3;
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uint32 reserved2 : 1;
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uint32 use_dyn_gear_sel : 1;
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uint32 gear_sel : 1;
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uint32 fs_bypass_en : 1;
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} Bits;
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uint32 Reg32;
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} BPCM_ZONE_N_FREQ_SCALAR_CONTROL;
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typedef struct
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{
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BPCM_PWR_ZONE_N_CONTROL control;
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BPCM_PWR_ZONE_N_CONFIG1 config1;
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BPCM_PWR_ZONE_N_CONFIG2 config2;
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BPCM_ZONE_N_FREQ_SCALAR_CONTROL freq_scalar_control;
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} BPCM_ZONE;
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// There is a 20-bit address used to access any given BPCM register. The upper 8-bits
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// is the device address and the lower 12-bits is used to represent the BPCM register
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// set for that device. 32-bit registers are allocated on 4-byte boundaries
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// (i.e. 0, 1, 2, 3...) rather than on byte boundaries (0x00, 0x04, 0x08, 0x0c...)
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// Thus, to get the actual address of any given register within the device's address
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// space, I'll use the "C" offsetof macro and divide the result by 4
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// e.g.:
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// int regOffset = offsetof(BPCM_REGS,BPCM_AVS_PWD_CONTROL); // yeilds the byte offset of the target register
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// int regAddress = regOffset/4; // yeilds the 32-bit offset of the target register
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// The ReadBPCMReg and WriteBPCMReg functions will always take a device address
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// (address of the BPCM device) and register offset (like regOffset above). The offset
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// will be divided by 4 and used as the lower 12-bits of the actual target address, while the
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// device address will serve as the upper 8-bits of the actual address.
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typedef struct
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{
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BPCM_ID_REG id_reg; // offset = 0x00, actual offset = 0
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BPCM_CAPABILITES_REG capabilities; // offset = 0x04, actual offset = 1
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uint32 control; // offset = 0x08, actual offset = 2
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BPCM_STATUS_REG status; // offset = 0x0c, actual offset = 3
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BPCM_AVS_ROSC_CONTROL_REG rosc_control; // offset = 0x10, actual offset = 4
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BPCM_AVS_ROSC_THRESHOLD rosc_threshold; // offset = 0x14, actual offset = 5
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BPCM_AVS_ROSC_COUNT rosc_count; // offset = 0x18, actual offset = 6
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BPCM_AVS_PWD_CONTROL pwd_control; // offset = 0x1c, actual offset = 7
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uint32 reseved[8]; // offset = 0x20, actual offset = 8..15
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BPCM_ZONE zones[1020]; // offset = 0x40..0x3FFC, actual offset = 16..4095 (1020 * 4 = 4080 + 16 = 4096)
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} BPCM_REGS; // total offset space = 4096
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// *************************** macros ******************************
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#define BPCMOffset(reg) offsetof(BPCM_REGS,reg)
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#endif
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