mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
synced 2025-05-19 07:51:46 +02:00
123 lines
2.8 KiB
Text
123 lines
2.8 KiB
Text
#define GIC_DIST_BASE 0x81001000
|
|
#define GIC_CPUI_BASE 0x81002000
|
|
|
|
#define TIMER_HYP_PPI 10
|
|
#define TIMER_VIRT_PPI 11
|
|
#define TIMER_PHYS_SECURE_PPI 13
|
|
#define TIMER_PHYS_NONSECURE_PPI 14
|
|
|
|
#define PMU_CORE0_SPI 9
|
|
#define PMU_CORE1_SPI 10
|
|
#define PMU_CORE2_SPI 11
|
|
#define PMU_CORE3_SPI 12
|
|
#define HS_SPIM_SPI 37
|
|
#define SDIO_EMMC_SPI 95
|
|
#define SPU_GMAC_SPI 118
|
|
|
|
#include "../bcm_b53_template.dtsi"
|
|
|
|
/ {
|
|
/* according to inclusion rules of device tree */
|
|
reserved-memory {
|
|
|
|
#if defined (CONFIG_OPTEE)
|
|
dt_reserved_optee {
|
|
reg = <0x0 0x10000000 0x0 0x01000000>;
|
|
no-map;
|
|
};
|
|
|
|
dt_reserved_tzioc {
|
|
reg = <0x0 0x11000000 0x0 0x00800000>;
|
|
};
|
|
#endif /* CONFIG_OPTEE */
|
|
|
|
#if defined (CONFIG_BCM_RDPA)
|
|
dt_reserved_fpm_pool {
|
|
reg = <0x00000000 DRAM_OFFSET_RDP_PARAM1 0x0 RDP_PARAM1_DDR_SIZE>; /* 32MB */
|
|
};
|
|
dt_reserved_rnr_tbls {
|
|
reg = <0x00000000 DRAM_OFFSET_RDP_PARAM2 0x0 RDP_PARAM2_DDR_SIZE>; /* 8MB */
|
|
no-map;
|
|
};
|
|
#endif
|
|
};
|
|
|
|
aliases {
|
|
spi1 = &hsspi; /* 0 = legacy, 1 = high speed */
|
|
};
|
|
|
|
/* this is actually the PLL but we have no clock framework */
|
|
hsspi_pll: hsspi-pll {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <400000000>;
|
|
};
|
|
|
|
/* Legacy UBUS base */
|
|
ubus@ff800000 {
|
|
nand@ff801800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "brcm,nand-bcm63xx", "brcm,brcmnand-v7.1";
|
|
reg = <0x0 0x1800 0x0 0x600>, <0x0 0x2000 0x0 0x10>;
|
|
reg-names = "nand", "nand-int-base";
|
|
status = "okay";
|
|
|
|
nandcs@0 {
|
|
compatible = "brcm,nandcs";
|
|
reg = <0>;
|
|
nand-on-flash-bbt;
|
|
};
|
|
|
|
};
|
|
|
|
watchdog@ff802780 {
|
|
compatible = "brcm,bcm96xxx-wdt";
|
|
reg = <0x0 0x2780 0x0 0x10>;
|
|
timeout-sec = <80>;
|
|
};
|
|
|
|
/* 6858 use second i2c bus for pon sfp i2c device */
|
|
i2c_0: i2c@ff85a800 {
|
|
compatible = "brcm,bcm63000-i2c";
|
|
reg = <0x0 0x5a800 0x0 0x60>;
|
|
};
|
|
|
|
/* not enabling the first i2c bus until pon sfp driver fix
|
|
the assumption that only one i2c bus in the system
|
|
i2c_1: i2c@ff802100 {
|
|
compatible = "brcm,bcm63000-i2c";
|
|
reg = <0x0 0x2100 0x0 0x60>;
|
|
};*/
|
|
hsspi: spi@0xff801000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "brcm,bcm6328-hsspi";
|
|
reg = <0x0 0x1000 0x0 0x600>;
|
|
clocks = <&hsspi_pll>, <&hsspi_pll>;
|
|
clock-names = "hsspi", "pll";
|
|
spi-max-frequency = <100000000>;
|
|
num-cs = <8>;
|
|
cs-gpios = <0>, <0>;
|
|
interrupts = <GIC_SPI HS_SPIM_SPI IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "okay";
|
|
};
|
|
};
|
|
|
|
pdc0: spu-pdc@0x8001c000 {
|
|
compatible = "brcm,pdc";
|
|
reg = <0x00000000 0x8001c000 0x00000000 0x448>;
|
|
interrupts = <GIC_SPI SPU_GMAC_SPI IRQ_TYPE_LEVEL_HIGH>;
|
|
brcm,num_chan = <1>;
|
|
};
|
|
|
|
spu-crypto@0x8001d000 {
|
|
compatible = "brcm,spu-crypto";
|
|
reg = <0x00000000 0x8001d000 0x00000000 0x64>;
|
|
brcm,num_spu = <1>;
|
|
};
|
|
|
|
};
|
|
|
|
|
|
|