mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
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270 lines
6.8 KiB
C
270 lines
6.8 KiB
C
/*
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* <:copyright-BRCM:2017:DUAL/GPL:standard
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*
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* Copyright (c) 2017 Broadcom
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* All Rights Reserved
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed
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* to you under the terms of the GNU General Public License version 2
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* (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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* with the following added to such license:
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*
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* As a special exception, the copyright holders of this software give
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* you permission to link this software with independent modules, and
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* to copy and distribute the resulting executable under terms of your
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* choice, provided that you also meet, for each linked independent
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* module, the terms and conditions of the license of that module.
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* An independent module is a module which is not derived from this
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* software. The special exception does not apply to any modifications
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* of the software.
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*
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* Not withstanding the above, under no circumstances may you combine
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* this software in any way with any other Broadcom software provided
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* under a license other than the GPL, without Broadcom's express prior
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* written consent.
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*
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* :>
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*/
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#include "boardparms.h"
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#ifdef _CFE_
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#include "lib_types.h"
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#include "lib_printf.h"
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#include "lib_string.h"
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#include "bcm_map.h"
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#define printk printf
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#endif
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#include "bcm_map_part.h"
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#ifndef _CFE_
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#include <linux/module.h>
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#endif
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#include "bcm_gpio.h"
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#include "bcm_bbsi.h"
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static int
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spi_write(struct bbsi_t *bbsi, uint8 *buf, uint32 buflen)
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{
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uint32 spi_clk = 1 << bbsi->spi_clk;
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uint32 spi_cs = 1 << bbsi->spi_cs;
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uint32 spi_mosi = 1 << bbsi->spi_mosi;
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uint32 i, j, output;
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uint8 data;
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/* set CS low (activate) */
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bcm_multi_gpio_set_data(spi_cs, 0);
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for (i = 0; i < buflen; i++) {
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data = buf[i];
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/* send data from MSB to LSB */
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for (j = 0; j < 8; j++) {
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output = (data & 0x80) ? spi_mosi : 0;
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/* clock falling and output data (mode 3) */
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bcm_multi_gpio_set_data(spi_clk | spi_mosi, 0 | output);
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/* clock rising */
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bcm_multi_gpio_set_data(spi_clk, spi_clk);
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/* shift to next bit to be send */
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data <<= 1;
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}
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}
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/* Set CS high (deactivate) */
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bcm_multi_gpio_set_data(spi_cs, spi_cs);
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return 0;
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}
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static int
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spi_write_then_read(struct bbsi_t *bbsi, uint8 *buf, uint32 buflen, uint8 *rbuf, uint32 rbuflen)
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{
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uint32 spi_clk = 1 << bbsi->spi_clk;
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uint32 spi_cs = 1 << bbsi->spi_cs;
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uint32 spi_mosi = 1 << bbsi->spi_mosi;
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uint32 i, j, output;
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uint8 data;
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/* set CS low (activate) */
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bcm_multi_gpio_set_data(spi_cs, 0);
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for (i = 0; i < buflen; i++) {
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data = buf[i];
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/* send data from MSB to LSB */
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for (j = 0; j < 8; j++) {
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output = (data & 0x80) ? spi_mosi : 0;
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/* clock falling and output data (mode 3) */
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bcm_multi_gpio_set_data((spi_clk | spi_mosi), output);
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/* clock rising */
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bcm_multi_gpio_set_data(spi_clk, spi_clk);
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/* shift to next bit to be send */
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data <<= 1;
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}
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}
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for (i = 0; i < rbuflen; i++) {
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/* receive data from MSB to LSB */
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for (j = 0, data = 0; j < 8; j++) {
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/* shift to next bit */
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data <<= 1;
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/* clock falling */
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bcm_multi_gpio_set_data(spi_clk, 0);
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/* sample input data */
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data |= bcm_gpio_get_data(bbsi->spi_miso);
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/* clock rising */
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bcm_multi_gpio_set_data(spi_clk, spi_clk);
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}
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rbuf[i] = data;
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}
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/* Set CS high (deactivate) */
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bcm_multi_gpio_set_data(spi_cs, spi_cs);
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return 0;
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}
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/* Poll for command completion. Returns zero when complete. */
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int is_bbsi_done(struct bbsi_t *bbsi)
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{
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uint8 read_status[2] = {BBSI_CMD_READ, BBSI_STATUS_REG_ADDR};
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uint8 read_rx;
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int status, i, ret = -1;
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for (i = 0; i < BSSI_STATUS_RETRY; i++) {
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/* issue command to spi */
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status = spi_write_then_read(bbsi, read_status, 2, &read_rx, 1);
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/* status return from spi operation */
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if (status != 0) {
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printk("%s: spi returned error\n", __func__);
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break;
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}
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/* transaction error reported by BBSI slave device */
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if (read_rx & BBSI_STATUS_FAILED) {
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printk("%s: BBSI transaction error, status=0x%x\n", __func__, read_rx);
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break;
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} else if ((read_rx & (1 << BBSI_STATUS_BUSY_SHIFT)) == 0) {
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/* transaction completed */
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ret = 0;
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break;
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}
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}
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return ret;
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}
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int bbsi_read(struct bbsi_t *bbsi, uint32_t addr, uint32_t readlen, uint32_t *data)
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{
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uint8 buf[7] = {0}, rbuf[4] = {0};
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int status, ret = -1;
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if (readlen > 4) {
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printk("%s: incorrect read length: %d\n", __func__, readlen);
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return ret;
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}
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buf[0] = BBSI_CMD_WRITE;
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buf[1] = BBSI_CONFIG_REG_ADDR;
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buf[2] = ((4 - readlen) << BBSI_CONFIG_XFER_MODE_SHIFT) |
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(BBSI_CONFIG_READ_RBUS_MASK << BBSI_CONFIG_READ_RBUS_SHIFT);
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buf[3] = (addr >> 24) & 0xFF; /* Assuming MSB bytes are always sent first */
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buf[4] = (addr >> 16) & 0xFF;
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buf[5] = (addr >> 8) & 0xFF;
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buf[6] = (addr >> 0) & 0xFF;
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status = spi_write(bbsi, buf, 7);
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if (status != 0) {
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printk("%s: Spi returned error\n", __func__);
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return ret;
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}
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if (is_bbsi_done(bbsi) != 0) {
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printk("%s: read to addr:0x%08x failed\n", __func__, addr);
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return ret;
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}
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buf[0] = BBSI_CMD_READ;
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buf[1] = BBSI_DATA0_REG_ADDR;
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status = spi_write_then_read(bbsi, buf, 2, rbuf, 4);
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if (status != 0) {
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printk("%s: spi returned error\n", __func__);
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return ret;
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}
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*data = (rbuf[0] << 24) | (rbuf[1] << 16) | (rbuf[2] << 8) | rbuf[3];
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ret = 0;
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return ret;
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}
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int bbsi_write(struct bbsi_t *bbsi, uint32 addr, uint32 writelen, uint32 data)
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{
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uint8 buf[12];
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int status, ret = -1;
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if (writelen > 4) {
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printk("%s: incorrect write length: %d\n", __func__, writelen);
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return ret;
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}
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data <<= (8 * (4 - writelen));
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buf[0] = BBSI_CMD_WRITE;
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buf[1] = BBSI_CONFIG_REG_ADDR;
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buf[2] = (4 - writelen) << BBSI_CONFIG_XFER_MODE_SHIFT;
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buf[3] = (addr >> 24) & 0xFF; /* Assuming MSB bytes are always sent first */
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buf[4] = (addr >> 16) & 0xFF;
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buf[5] = (addr >> 8) & 0xFF;
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buf[6] = (addr >> 0) & 0xFF;
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buf[7] = (data >> 24) & 0xFF;
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buf[8] = (data >> 16) & 0xFF;
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buf[9] = (data >> 8) & 0xFF;
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buf[10] = (data >> 0) & 0xFF;
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status = spi_write(bbsi, buf, 11);
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if (status != 0) {
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printk("%s: Spi returned error\n", __func__);
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return ret;
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}
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if (is_bbsi_done(bbsi) != 0) {
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printk("%s: write to addr:0x%08x failed\n", __func__, addr);
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return ret;
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}
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ret = 0;
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return ret;
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}
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void bbsi_init(struct bbsi_t *bbsi)
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{
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uint32_t mask, val;
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/* BCM6802 need spi on mode3. set clk, cs to 1, mosi to 0 */
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mask = (1 << bbsi->spi_clk) | (1 << bbsi->spi_cs) | (1 << bbsi->spi_mosi);
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val = (1 << bbsi->spi_clk) | (1 << bbsi->spi_cs);
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bcm_multi_gpio_set_data(mask, val);
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/* Setup GPIO output */
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mask = (1 << bbsi->spi_clk) | (1 << bbsi->spi_mosi) | (1 << bbsi->spi_cs);
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val = (1 << bbsi->spi_clk) | (1 << bbsi->spi_mosi) | (1 << bbsi->spi_cs);
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bcm_multi_gpio_set_dir(mask, val);
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}
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#ifndef _CFE_
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EXPORT_SYMBOL(bbsi_init);
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EXPORT_SYMBOL(bbsi_write);
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EXPORT_SYMBOL(bbsi_read);
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EXPORT_SYMBOL(is_bbsi_done);
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#endif
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