mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
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325 lines
19 KiB
C
Executable file
325 lines
19 KiB
C
Executable file
/*
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<:copyright-BRCM:2012:DUAL/GPL:standard
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Copyright (c) 2012 Broadcom
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All Rights Reserved
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Unless you and Broadcom execute a separate written software license
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agreement governing use of this software, this software is licensed
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to you under the terms of the GNU General Public License version 2
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(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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with the following added to such license:
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As a special exception, the copyright holders of this software give
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you permission to link this software with independent modules, and
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to copy and distribute the resulting executable under terms of your
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choice, provided that you also meet, for each linked independent
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module, the terms and conditions of the license of that module.
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An independent module is a module which is not derived from this
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software. The special exception does not apply to any modifications
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of the software.
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Not withstanding the above, under no circumstances may you combine
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this software in any way with any other Broadcom software provided
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under a license other than the GPL, without Broadcom's express prior
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written consent.
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:>
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*/
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#ifndef __6836_INTR_H
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#define __6836_INTR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*=====================================================================*/
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/* SPI Table Offset */
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/*=====================================================================*/
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#define SPI_TABLE_OFFSET 32
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/*=====================================================================*/
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/* Physical Interrupt IDs */
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/*=====================================================================*/
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/* ------------- CHIP_IRQS[31-0] ----------------------------*/
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#define INTERRUPT_B53_AXIERRIRQ (SPI_TABLE_OFFSET + 0)
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#define INTERRUPT_B53_INTERRIRQ (SPI_TABLE_OFFSET + 1)
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//#define INTERRUPT_B53_ACCESS_VIOL0_IRQ (SPI_TABLE_OFFSET + 2)
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//#define INTERRUPT_B53_ACCESS_VIOL1_IRQ (SPI_TABLE_OFFSET + 3)
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#define INTERRUPT_B53_CCIERRIRQ (SPI_TABLE_OFFSET + 4)
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#define INTERRUPT_B53_CCIOVFLOWIRQ (SPI_TABLE_OFFSET + 5)
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#define INTERRUPT_THERM_HIGH_IRQ (SPI_TABLE_OFFSET + 6)
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#define INTERRUPT_THERM_LOW_IRQ (SPI_TABLE_OFFSET + 7)
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#define INTERRUPT_THERM_SHUTDOWN (SPI_TABLE_OFFSET + 8)
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#define INTERRUPT_PMUIRQ (SPI_TABLE_OFFSET + 9) /* 2 interrupts */
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/* 2 reserved interrupts */
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#define INTERRUPT_PER_TIMER_IRQ0 (SPI_TABLE_OFFSET + 12)
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#define INTERRUPT_PER_TIMER_IRQ1 (SPI_TABLE_OFFSET + 13)
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#define INTERRUPT_PER_TIMER_IRQ2 (SPI_TABLE_OFFSET + 14)
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#define INTERRUPT_PER_TIMER_IRQ3 (SPI_TABLE_OFFSET + 15)
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#define INTERRUPT_B53_COMMONIRQ (SPI_TABLE_OFFSET + 17)
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#define INTERRUPT_MEMC_SEC_IRQ (SPI_TABLE_OFFSET + 18)
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#define INTERRUPT_ORION_INT_PENDING (SPI_TABLE_OFFSET + 19)
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#define INTERRUPT_PER_SEC_ACC_VIOL_IRQ (SPI_TABLE_OFFSET + 20)
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#define INTERRUPT_B53_UBUS_RC_IRQ (SPI_TABLE_OFFSET + 21)
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#define INTERRUPT_B53_UBUS_STAT_REG (SPI_TABLE_OFFSET + 22)
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#define INTERRUPT_SPU_GMAC_IRQ (SPI_TABLE_OFFSET + 23)
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#define INTERRUPT_SPU_CTF_IRQ (SPI_TABLE_OFFSET + 24)
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/* 3 reserved interrupts */
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#define INTERRUPT_PMC_TEMP_WARN (SPI_TABLE_OFFSET + 28)
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#define INTERRUPT_DYING_GASP_IRQ (SPI_TABLE_OFFSET + 29)
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#define INTERRUPT_PMC_MIPS_IRQ (SPI_TABLE_OFFSET + 30)
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#define INTERRUPT_PMC_MIPS1_IRQ (SPI_TABLE_OFFSET + 31)
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#define INTERRUPT_PER_UARTINT0 (SPI_TABLE_OFFSET + 32)
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#define INTERRUPT_PER_UARTINT1 (SPI_TABLE_OFFSET + 33)
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/* 2 reserved interrupts */
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#define INTERRUPT_PER_DMA_IRQ (SPI_TABLE_OFFSET + 36)
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#define INTERRUPT_PER_HS_SPIM_IRQ (SPI_TABLE_OFFSET + 37)
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#define INTERRUPT_NAND_FLASH_IRQ (SPI_TABLE_OFFSET + 38)
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#define INTERRUPT_MEMC_IRQ (SPI_TABLE_OFFSET + 39)
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/* 4 reserved interrupts */
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#define INTERRUPT_SATA_CPU_INTR0 (SPI_TABLE_OFFSET + 44)
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#define INTERRUPT_SATA_CPU_INTR1 (SPI_TABLE_OFFSET + 45)
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/* 4 reserved interrupts */
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#define INTERRUPT_MAC_QEGPHY_CFG_IRQ (SPI_TABLE_OFFSET + 50) /* 4 interrupts */
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/* 6 reserved interrupts */
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#define INTERRUPT_PCIE_0_CPU_INTR (SPI_TABLE_OFFSET + 60)
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#define INTERRUPT_PCIE_1_CPU_INTR (SPI_TABLE_OFFSET + 61)
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#define INTERRUPT_PCIE_2_CPU_INTR (SPI_TABLE_OFFSET + 62)
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#define INTERRUPT_UBUS4_SYS_IRQ (SPI_TABLE_OFFSET + 63)
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/* 4 reserved interrupts */
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#define INTERRUPT_MBOX_IRQ0_3 (SPI_TABLE_OFFSET + 68) /* 4 interrupts */
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#define INTERRUPT_PERIPH_INTERNAL0 (SPI_TABLE_OFFSET + 72) /* 5 interrupts */
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/* 6 reserved interrupts */
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#define INTERRUPT_PER_I2C_IRQ (SPI_TABLE_OFFSET + 83)
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#define INTERRUPT_PER_I2S_IRQ (SPI_TABLE_OFFSET + 84)
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#define INTERRUPT_O_RNG_INTR (SPI_TABLE_OFFSET + 85)
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/* 3 reserved interrupts */
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#define INTERRUPT_SGMII_SIGDET_IRQ (SPI_TABLE_OFFSET + 89)
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/* 3 reserved interrupts */
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#define INTERRUPT_PER_HS_UARTINT (SPI_TABLE_OFFSET + 93)
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#define INTERRUPT_PL081_DMA_INTR (SPI_TABLE_OFFSET + 94)
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#define INTERRUPT_SDIO_EMMC_L1_INTR (SPI_TABLE_OFFSET + 95)
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#define INTERRUPT_WAN_EPON_TOP (SPI_TABLE_OFFSET + 96)
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#define INTERRUPT_WAN_NCO_GPON (SPI_TABLE_OFFSET + 97)
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#define INTERRUPT_WAN_GPON_TX (SPI_TABLE_OFFSET + 98)
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#define INTERRUPT_WAN_GPON_RX (SPI_TABLE_OFFSET + 99)
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#define INTERRUPT_WAN_PMD_PLL1_LOCK_INT (SPI_TABLE_OFFSET + 100)
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#define INTERRUPT_WAN_PMD_PLL0_LOCK_INT (SPI_TABLE_OFFSET + 101)
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#define INTERRUPT_WAN_PMD_SIGNAL_DETECT_0 (SPI_TABLE_OFFSET + 102)
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#define INTERRUPT_WAN_PMD_ENERGY_DETECT_0 (SPI_TABLE_OFFSET + 103)
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#define INTERRUPT_WAN_PMD_RX_LOCK_0 (SPI_TABLE_OFFSET + 104)
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/* 7 reserved interrupts */
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#define INTERRUPT_PER_SIM (SPI_TABLE_OFFSET + 111) /* 3 interrupts */
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#define INTERRUPT_PCM_DMA_IRQ0 (SPI_TABLE_OFFSET + 114) /* PCM DMA RX interrupt */
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#define INTERRUPT_PCM_DMA_IRQ1 (SPI_TABLE_OFFSET + 115) /* PCM DMA TX interrupt */
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#define INTERRUPT_PCM_IRQ (SPI_TABLE_OFFSET + 116) /* 2 interrupts */
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#define INTERRUPT_PER_MDIO_ERR_IRQ (SPI_TABLE_OFFSET + 118)
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#define INTERRUPT_PER_MDIO_DONE_IRQ (SPI_TABLE_OFFSET + 119)
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#define INTERRUPT_USB_USBD (SPI_TABLE_OFFSET + 120)
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#define INTERRUPT_USB_XHCI (SPI_TABLE_OFFSET + 121)
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#define INTERRUPT_USB_OHCI1 (SPI_TABLE_OFFSET + 122)
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#define INTERRUPT_USB_EHCI1 (SPI_TABLE_OFFSET + 123)
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#define INTERRUPT_USB_OHCI (SPI_TABLE_OFFSET + 123)
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#define INTERRUPT_USB_EHCI (SPI_TABLE_OFFSET + 125)
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#define INTERRUPT_USB_EVENTS (SPI_TABLE_OFFSET + 126)
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#define INTERRUPT_USB_BRIDGE ( SPI_TABLE_OFFSET + 127)
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#define INTERRUPT_XRDP_QUEUE_0 (SPI_TABLE_OFFSET + 128)
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#define INTERRUPT_XRDP_QUEUE_1 (SPI_TABLE_OFFSET + 129)
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#define INTERRUPT_XRDP_QUEUE_2 (SPI_TABLE_OFFSET + 130)
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#define INTERRUPT_XRDP_QUEUE_3 (SPI_TABLE_OFFSET + 131)
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#define INTERRUPT_XRDP_QUEUE_4 (SPI_TABLE_OFFSET + 132)
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#define INTERRUPT_XRDP_QUEUE_5 (SPI_TABLE_OFFSET + 133)
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#define INTERRUPT_XRDP_QUEUE_6 (SPI_TABLE_OFFSET + 134)
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#define INTERRUPT_XRDP_QUEUE_7 (SPI_TABLE_OFFSET + 135)
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#define INTERRUPT_XRDP_QUEUE_8 (SPI_TABLE_OFFSET + 136)
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#define INTERRUPT_XRDP_QUEUE_9 (SPI_TABLE_OFFSET + 137)
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#define INTERRUPT_XRDP_QUEUE_10 (SPI_TABLE_OFFSET + 138)
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#define INTERRUPT_XRDP_QUEUE_11 (SPI_TABLE_OFFSET + 139)
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#define INTERRUPT_XRDP_QUEUE_12 (SPI_TABLE_OFFSET + 140)
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#define INTERRUPT_XRDP_QUEUE_13 (SPI_TABLE_OFFSET + 141)
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#define INTERRUPT_XRDP_QUEUE_14 (SPI_TABLE_OFFSET + 142)
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#define INTERRUPT_XRDP_QUEUE_15 (SPI_TABLE_OFFSET + 143)
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#define INTERRUPT_XRDP_QUEUE_16 (SPI_TABLE_OFFSET + 144)
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#define INTERRUPT_XRDP_QUEUE_17 (SPI_TABLE_OFFSET + 145)
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#define INTERRUPT_XRDP_QUEUE_18 (SPI_TABLE_OFFSET + 146)
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#define INTERRUPT_XRDP_QUEUE_19 (SPI_TABLE_OFFSET + 147)
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#define INTERRUPT_XRDP_QUEUE_20 (SPI_TABLE_OFFSET + 148)
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#define INTERRUPT_XRDP_QUEUE_21 (SPI_TABLE_OFFSET + 149)
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#define INTERRUPT_XRDP_QUEUE_22 (SPI_TABLE_OFFSET + 150)
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#define INTERRUPT_XRDP_QUEUE_23 (SPI_TABLE_OFFSET + 151)
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#define INTERRUPT_XRDP_QUEUE_24 (SPI_TABLE_OFFSET + 152)
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#define INTERRUPT_XRDP_QUEUE_25 (SPI_TABLE_OFFSET + 153)
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#define INTERRUPT_XRDP_QUEUE_26 (SPI_TABLE_OFFSET + 154)
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#define INTERRUPT_XRDP_QUEUE_27 (SPI_TABLE_OFFSET + 155)
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#define INTERRUPT_XRDP_QUEUE_28 (SPI_TABLE_OFFSET + 156)
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#define INTERRUPT_XRDP_QUEUE_29 (SPI_TABLE_OFFSET + 157)
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#define INTERRUPT_XRDP_QUEUE_30 (SPI_TABLE_OFFSET + 158)
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#define INTERRUPT_XRDP_QUEUE_31 (SPI_TABLE_OFFSET + 159)
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#define INTERRUPT_PER_EXT_0 (SPI_TABLE_OFFSET + 181)
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#define INTERRUPT_PER_EXT_1 (SPI_TABLE_OFFSET + 182)
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#define INTERRUPT_PER_EXT_2 (SPI_TABLE_OFFSET + 183)
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#define INTERRUPT_PER_EXT_3 (SPI_TABLE_OFFSET + 184)
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#define INTERRUPT_PER_EXT_4 (SPI_TABLE_OFFSET + 185)
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#define INTERRUPT_PER_EXT_5 (SPI_TABLE_OFFSET + 186)
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#define INTERRUPT_PER_EXT_6 (SPI_TABLE_OFFSET + 187)
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#define INTERRUPT_PER_EXT_7 (SPI_TABLE_OFFSET + 188)
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#ifndef __ASSEMBLER__
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/*=====================================================================*/
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/* Linux(Virtual) Interrupt IDs */
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/* Each physical irq id to be mapped should be added to */
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/* bcm_phys_irqs_to_map array in board_aarch64.c file */
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/*=====================================================================*/
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#define INTERRUPT_ID_DG (bcm_legacy_irq_map[INTERRUPT_DYING_GASP_IRQ - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_UART (bcm_legacy_irq_map[INTERRUPT_PER_UARTINT0 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_UART1 (bcm_legacy_irq_map[INTERRUPT_PER_UARTINT1 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_HS_UART (bcm_legacy_irq_map[INTERRUPT_PER_HS_UARTINT - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_SATAC (bcm_legacy_irq_map[INTERRUPT_SATA_CPU_INTR0 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_PCIE0 (bcm_legacy_irq_map[INTERRUPT_PCIE_0_CPU_INTR - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_PCIE1 (bcm_legacy_irq_map[INTERRUPT_PCIE_1_CPU_INTR - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_PCIE2 (bcm_legacy_irq_map[INTERRUPT_PCIE_2_CPU_INTR - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_TIMER0 (bcm_legacy_irq_map[INTERRUPT_PER_TIMER_IRQ0 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_TIMER INTERRUPT_ID_TIMER0
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#define INTERRUPT_ID_TIMER1 (bcm_legacy_irq_map[INTERRUPT_PER_TIMER_IRQ1 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_TIMER2 (bcm_legacy_irq_map[INTERRUPT_PER_TIMER_IRQ2 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_TIMER3 (bcm_legacy_irq_map[INTERRUPT_PER_TIMER_IRQ3 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_TIMER_MAX INTERRUPT_ID_TIMER3
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#define INTERRUPT_ID_EXTERNAL_0 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_0 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_1 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_1 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_2 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_2 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_3 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_3 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_4 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_4 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_5 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_5 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_6 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_6 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_7 (bcm_legacy_irq_map[INTERRUPT_PER_EXT_7 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_EXTERNAL_MAX INTERRUPT_ID_EXTERNAL_7
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#define INTERRUPT_ID_I2S (bcm_legacy_irq_map[INTERRUPT_PER_I2S_IRQ - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_USB_XHCI (bcm_legacy_irq_map[INTERRUPT_USB_XHCI - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_USB_OHCI (bcm_legacy_irq_map[INTERRUPT_USB_OHCI - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_USB_EHCI (bcm_legacy_irq_map[INTERRUPT_USB_EHCI - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_USB_OHCI1 (bcm_legacy_irq_map[INTERRUPT_USB_OHCI1 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_USB_EHCI1 (bcm_legacy_irq_map[INTERRUPT_USB_EHCI1 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_NAND_FLASH (bcm_legacy_irq_map[INTERRUPT_NAND_FLASH_IRQ - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_WAN_GPON_RX (bcm_legacy_irq_map[INTERRUPT_WAN_GPON_RX - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_WAN_GPON_TX (bcm_legacy_irq_map[INTERRUPT_WAN_GPON_TX - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_0 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_0 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_1 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_1 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_2 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_2 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_3 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_3 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_4 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_4 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_5 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_5 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_6 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_6 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_7 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_7 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_8 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_8 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_9 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_9- SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_10 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_10 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_11 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_11 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_12 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_12 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_13 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_13 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_14 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_14 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_15 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_15 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_16 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_16 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_17 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_17 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_18 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_18 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_19 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_19 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_20 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_20 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_21 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_21 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_22 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_22 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_23 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_23 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_24 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_24 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_25 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_25 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_26 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_26 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_27 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_27 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_28 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_28 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_39 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_29 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_30 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_30 - SPI_TABLE_OFFSET])
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#define INTERRUPT_ID_XRDP_QUEUE_31 (bcm_legacy_irq_map[INTERRUPT_XRDP_QUEUE_31 - SPI_TABLE_OFFSET])
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#define INTERRUPT_PCM_DMA_IRQ (bcm_legacy_irq_map[INTERRUPT_PCM_DMA_IRQ0 - SPI_TABLE_OFFSET])
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#ifdef __BOARD_DRV_AARCH64__
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// add here any legacy driver's (driver that have no device tree node) interrupt to be mapped
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unsigned int bcm_phys_irqs_to_map[] =
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{
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INTERRUPT_DYING_GASP_IRQ,
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INTERRUPT_PER_UARTINT0,
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INTERRUPT_PER_UARTINT1,
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INTERRUPT_PER_HS_UARTINT,
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INTERRUPT_PCIE_0_CPU_INTR,
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INTERRUPT_PCIE_1_CPU_INTR,
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INTERRUPT_PCIE_2_CPU_INTR,
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INTERRUPT_PER_TIMER_IRQ0,
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INTERRUPT_PER_TIMER_IRQ1,
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INTERRUPT_PER_TIMER_IRQ2,
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INTERRUPT_PER_TIMER_IRQ3,
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INTERRUPT_PER_EXT_0,
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INTERRUPT_PER_EXT_1,
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INTERRUPT_PER_EXT_2,
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INTERRUPT_PER_EXT_3,
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INTERRUPT_PER_EXT_4,
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INTERRUPT_PER_EXT_5,
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INTERRUPT_PER_EXT_6,
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INTERRUPT_PER_EXT_7,
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INTERRUPT_NAND_FLASH_IRQ,
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INTERRUPT_PER_I2S_IRQ,
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INTERRUPT_WAN_GPON_RX,
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INTERRUPT_WAN_GPON_TX,
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INTERRUPT_XRDP_QUEUE_0,
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INTERRUPT_XRDP_QUEUE_1,
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INTERRUPT_XRDP_QUEUE_2,
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INTERRUPT_XRDP_QUEUE_3,
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INTERRUPT_XRDP_QUEUE_4,
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INTERRUPT_XRDP_QUEUE_5,
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INTERRUPT_XRDP_QUEUE_6,
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INTERRUPT_XRDP_QUEUE_7,
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INTERRUPT_XRDP_QUEUE_8,
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INTERRUPT_XRDP_QUEUE_9,
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INTERRUPT_XRDP_QUEUE_10,
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INTERRUPT_XRDP_QUEUE_11,
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INTERRUPT_XRDP_QUEUE_12,
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INTERRUPT_XRDP_QUEUE_13,
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INTERRUPT_XRDP_QUEUE_14,
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INTERRUPT_XRDP_QUEUE_15,
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INTERRUPT_XRDP_QUEUE_16,
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INTERRUPT_XRDP_QUEUE_17,
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INTERRUPT_XRDP_QUEUE_18,
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INTERRUPT_XRDP_QUEUE_19,
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INTERRUPT_XRDP_QUEUE_20,
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INTERRUPT_XRDP_QUEUE_21,
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INTERRUPT_XRDP_QUEUE_22,
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INTERRUPT_XRDP_QUEUE_23,
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INTERRUPT_XRDP_QUEUE_24,
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INTERRUPT_XRDP_QUEUE_25,
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INTERRUPT_XRDP_QUEUE_26,
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INTERRUPT_XRDP_QUEUE_27,
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INTERRUPT_XRDP_QUEUE_28,
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INTERRUPT_XRDP_QUEUE_29,
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INTERRUPT_XRDP_QUEUE_30,
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INTERRUPT_XRDP_QUEUE_31,
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INTERRUPT_PCM_DMA_IRQ0,
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|
INTERRUPT_USB_XHCI,
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|
INTERRUPT_USB_OHCI,
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INTERRUPT_USB_EHCI,
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INTERRUPT_USB_OHCI1,
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|
INTERRUPT_USB_EHCI1
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|
};
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unsigned int bcm_legacy_irq_map[256];
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#else
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extern unsigned int bcm_phys_irqs_to_map[];
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extern unsigned int bcm_legacy_irq_map[];
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#endif
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|
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|
#endif
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|
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#define NUM_EXT_INT (INTERRUPT_PER_EXT_7-INTERRUPT_PER_EXT_0+1)
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|
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#ifdef __cplusplus
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|
}
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#endif
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|
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#endif /* __BCM6836_H */
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|