mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
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261 lines
8.1 KiB
C
261 lines
8.1 KiB
C
/*
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* <:copyright-BRCM:2017:DUAL/GPL:standard
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*
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* Copyright (c) 2017 Broadcom
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* All Rights Reserved
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed
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* to you under the terms of the GNU General Public License version 2
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* (the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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* with the following added to such license:
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*
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* As a special exception, the copyright holders of this software give
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* you permission to link this software with independent modules, and
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* to copy and distribute the resulting executable under terms of your
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* choice, provided that you also meet, for each linked independent
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* module, the terms and conditions of the license of that module.
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* An independent module is a module which is not derived from this
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* software. The special exception does not apply to any modifications
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* of the software.
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*
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* Not withstanding the above, under no circumstances may you combine
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* this software in any way with any other Broadcom software provided
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* under a license other than the GPL, without Broadcom's express prior
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* written consent.
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*
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* :>
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*/
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#ifndef __BCM_UBUS4_H__
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#define __BCM_UBUS4_H__
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#include <bcm_map_part.h>
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typedef struct ub_mst_addr_map_t {
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int port_id;
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unsigned long base;
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} ub_mst_addr_map_t;
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#if defined (CONFIG_BCM96858) || defined(_BCM96858_)
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#define UCB_NODE_ID_SLV_SYS 0
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#define UCB_NODE_ID_MST_PCIE0 3
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#define UCB_NODE_ID_SLV_PCIE0 4
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#define UCB_NODE_ID_MST_PCIE2 5
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#define UCB_NODE_ID_SLV_PCIE2 6
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#define UCB_NODE_ID_MST_SATA UCB_NODE_ID_MST_PCIE2
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#define UCB_NODE_ID_SLV_SATA UCB_NODE_ID_SLV_PCIE2
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#define UCB_NODE_ID_MST_USB 14
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#define UCB_NODE_ID_SLV_USB 15
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#define UCB_NODE_ID_SLV_LPORT 19
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#define UCB_NODE_ID_SLV_WAN 21
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int ubus_master_set_rte_addr(int master_port_id, int port, int val);
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#endif
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#if defined(CONFIG_BCM96856) || defined(_BCM96856_)
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#define UCB_NODE_ID_SLV_SYS 0
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#define UCB_NODE_ID_MST_PCIE0 3
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#define UCB_NODE_ID_SLV_PCIE0 4
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#define UCB_NODE_ID_MST_USB 14
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#define UCB_NODE_ID_SLV_USB 15
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#define UCB_NODE_ID_SLV_MEMC 16
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#elif defined(CONFIG_BCM96846) || defined(_BCM96846_)
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#define UCB_NODE_ID_MST_PCIE0 3
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#define UCB_NODE_ID_SLV_PCIE0 4
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#define UCB_NODE_ID_MST_USB 14
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#define UCB_NODE_ID_SLV_USB 15
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#define UCB_NODE_ID_SLV_MEMC 16
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#endif
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#if defined(CONFIG_BCM96846) || defined(_BCM96846_) || defined (CONFIG_BCM96856) || defined(_BCM96856_)
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extern unsigned int g_board_size_power_of_2;
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#endif
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#if defined (CONFIG_BCM963158) || defined(_BCM963158_)
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#define UBUS_MAX_PORT_NUM 32
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#define UBUS_NUM_OF_MST_PORTS 17
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#define UBUS_PORT_ID_LAST_SYSTOP 13
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#define UBUS_PORT_ID_BIU 2
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#define UBUS_PORT_ID_DMA0 24
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#define UBUS_PORT_ID_DQM 23
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#define UBUS_PORT_ID_DSLCPU 11
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#define UBUS_PORT_ID_DSL 6
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#define UBUS_PORT_ID_FPM 21
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#define UBUS_PORT_ID_MEMC 1
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#define UBUS_PORT_ID_NATC 26
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#define UBUS_PORT_ID_PCIE0 8
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#define UBUS_PORT_ID_PCIE2 9
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#define UBUS_PORT_ID_PCIE3 10
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#define UBUS_PORT_ID_PERDMA 7
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#define UBUS_PORT_ID_PER 3
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#define UBUS_PORT_ID_PMC 13
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#define UBUS_PORT_ID_PSRAM 16
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#define UBUS_PORT_ID_QM 22
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#define UBUS_PORT_ID_RQ0 32
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#define UBUS_PORT_ID_SPU 5
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#define UBUS_PORT_ID_SWH 14
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#define UBUS_PORT_ID_SYS 31
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#define UBUS_PORT_ID_SYSXRDP 27
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#define UBUS_PORT_ID_USB 4
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#define UBUS_PORT_ID_VPB 20
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#define UBUS_PORT_ID_WAN 12
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#elif defined (CONFIG_BCM96858) || defined(_BCM96858_)
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#define UBUS_MAX_PORT_NUM 35
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#define UBUS_NUM_OF_MST_PORTS 19
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#define UBUS_PORT_ID_LAST_SYSTOP 15
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#define UBUS_PORT_ID_MEMC 1
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#define UBUS_PORT_ID_BIU 2
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#define UBUS_PORT_ID_PER 3
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#define UBUS_PORT_ID_USB 4
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#define UBUS_PORT_ID_PERDMA 5
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#define UBUS_PORT_ID_SPU 6
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#define UBUS_PORT_ID_PCIE0 8
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#define UBUS_PORT_ID_PCIE2 9
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#define UBUS_PORT_ID_PMC 15
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#define UBUS_PORT_ID_XRDP_VPB 20
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#define UBUS_PORT_ID_QM 22
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#define UBUS_PORT_ID_DQM 23
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#define UBUS_PORT_ID_DMA0 24
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#define UBUS_PORT_ID_DMA1 25
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#define UBUS_PORT_ID_NATC 26
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#define UBUS_PORT_ID_TOP_BUFF 28
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#define UBUS_PORT_ID_XRDP_BUFF 29
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#define UBUS_PORT_ID_RQ0 32
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#define UBUS_PORT_ID_RQ1 33
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#define UBUS_PORT_ID_RQ2 34
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#define UBUS_PORT_ID_RQ3 35
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#elif defined (CONFIG_BCM96846) || defined(_BCM96846_)
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#define UBUS_MAX_PORT_NUM 15
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#define UBUS_NUM_OF_MST_PORTS 9
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#define UBUS_PORT_ID_LAST_SYSTOP 7
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#define UBUS_PORT_ID_MEMC 1
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#define UBUS_PORT_ID_BIU 2
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#define UBUS_PORT_ID_PER 3
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#define UBUS_PORT_ID_USB 4
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#define UBUS_PORT_ID_PCIE0 7
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#define UBUS_PORT_ID_QM 11
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#define UBUS_PORT_ID_DQM 12
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#define UBUS_PORT_ID_DMA0 13
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#define UBUS_PORT_ID_NATC 14
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#define UBUS_PORT_ID_RQ0 15
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#elif defined (CONFIG_BCM96856) || defined(_BCM96856_)
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#define UBUS_MAX_PORT_NUM 19
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#define UBUS_NUM_OF_MST_PORTS 12
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#define UBUS_PORT_ID_LAST_SYSTOP 7
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#define UBUS_PORT_ID_MEMC 1
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#define UBUS_PORT_ID_BIU 2
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#define UBUS_PORT_ID_PER 3
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#define UBUS_PORT_ID_USB 4
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#define UBUS_PORT_ID_PCIE2 6
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#define UBUS_PORT_ID_PCIE0 7
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#define UBUS_PORT_ID_QM 11
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#define UBUS_PORT_ID_DQM 12
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#define UBUS_PORT_ID_DMA0 13
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#define UBUS_PORT_ID_NATC 14
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#define UBUS_PORT_ID_DMA1 17
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#define UBUS_PORT_ID_RQ0 18
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#define UBUS_PORT_ID_RQ1 19
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#endif
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#ifdef CONFIG_BCM_GLB_COHERENCY
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#define IS_DDR_COHERENT 1
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#else
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#define IS_DDR_COHERENT 0
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#endif
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#define DECODE_CFG_SIZE_MASK 0xff00
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#define DECODE_CFG_SIZE_SHIFT 8
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#define DECODE_CFG_ENABLE_MASK 0x60000
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#define DECODE_CFG_ENABLE_SHIFT 17
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#define DECODE_CFG_CACHE_BITS_MASK 0x380000
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#define DECODE_CFG_CACHE_BITS_SHIFT 19
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#define DECODE_CFG_CMD_DTA_MASK 0x10000
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#define DECODE_CFG_CMD_DTA_SHIFT 16
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#define DECODE_CFG_STRICT_MASK 0x400000
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#define DECODE_CFG_STRICT_SHIFT 22
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#define DECODE_CFG_PORT_ID_MASK 0xff
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#define DECODE_CFG_PORT_ID_SHIFT 0
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#define DECODE_CFG_CTRL_CACHE_SEL_SHIFT 4
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#define DECODE_CFG_CTRL_CACHE_SEL_MASK (0x3<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
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#define DECODE_CFG_ENABLE_OFF (0 << DECODE_CFG_ENABLE_SHIFT)
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#define DECODE_CFG_ENABLE_ADDR_ONLY (1 << DECODE_CFG_ENABLE_SHIFT)
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#define DECODE_CFG_ENABLE_CDSM_0 (2 << DECODE_CFG_ENABLE_SHIFT)
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#define DECODE_CFG_ENABLE_CDSM_1 (3 << DECODE_CFG_ENABLE_SHIFT)
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#define DECODE_CFG_CACHE_BITS (1 << DECODE_CFG_CACHE_BITS_SHIFT)
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#define DECODE_CFG_CTRL_CACHE_SEL_DEF (0x0<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
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#define DECODE_CFG_CTRL_CACHE_SEL_INPUT (0x1<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
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#define DECODE_CFG_CTRL_CACHE_SEL_CFG_REG (0x2<<DECODE_CFG_CTRL_CACHE_SEL_SHIFT)
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/**
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* m = memory, f = field
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*/
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#define GET_FIELD(m,f) \
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(((m) & f##_MASK) >> f##_SHIFT)
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typedef struct
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{
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uint32 base_addr;
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uint32 remap_addr;
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uint32 attributes;
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}DecodeCfgMstWndRegs;
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/* BIU Registers */
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/* not relevant for 6846 platform but stil compile in pon stack */
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#define NGPON2_IDX 0
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typedef struct
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{
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uint32 ctrl;
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uint32 cache_cfg;
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uint32 reserved[2];
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DecodeCfgMstWndRegs window[4];
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} DecodeCfgRegs;
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typedef struct
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{
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uint32 port_cfg[8];
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#define DCM_UBUS_CONGESTION_THRESHOLD 3
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uint32 reserved1[56];
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uint32 loopback[20];
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uint32 reserved2[44];
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uint32 routing_addr[128];
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uint32 token[128];
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DecodeCfgRegs decode_cfg;
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} MstPortNode;
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typedef struct ubus_credit_cfg {
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int port_id;
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int credit;
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}ubus_credit_cfg_t;
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void ubus_master_port_init(void);
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void bcm_ubus_config(void);
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void ubus_cong_threshold_wr(int port_id, unsigned int val);
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int ubus_master_remap_port(int master_port_id);
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int log2_32 (unsigned int value);
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int ubus_master_set_token_credits(int master_port_id, int token, int credits);
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void ubus_deregister_port(int ucbid);
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void ubus_register_port(int ucbid);
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#if defined(CONFIG_BCM963158) || defined(CONFIG_BCM96858)
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void apply_ubus_credit_each_master(int master);
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#endif
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#if defined(_BCM96858_)
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void ubus_master_rte_cfg(void);
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#endif
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#endif
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