mirror of
https://github.com/gnuton/asuswrt-merlin.ng.git
synced 2025-05-19 07:51:46 +02:00
359 lines
14 KiB
C
359 lines
14 KiB
C
/* *********************************************************************
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* Broadcom Common Firmware Environment (CFE)
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*
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* MII register definitions File: mii.h
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*
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* Register and bit definitions for the standard MII management
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* interface.
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*
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* Author: Mitch Lichtenberg (mpl@broadcom.com)
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*
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*********************************************************************
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*
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* Copyright 2000,2001,2002,2003
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* Broadcom Corporation. All rights reserved.
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*
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* This software is furnished under license and may be used and
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* copied only in accordance with the following terms and
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* conditions. Subject to these conditions, you may download,
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* copy, install, use, modify and distribute modified or unmodified
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* copies of this software in source and/or binary form. No title
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* or ownership is transferred hereby.
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*
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* 1) Any source code used, modified or distributed must reproduce
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* and retain this copyright notice and list of conditions
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* as they appear in the source file.
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*
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* 2) No right is granted to use any trade name, trademark, or
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* logo of Broadcom Corporation. The "Broadcom Corporation"
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* name may not be used to endorse or promote products derived
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* from this software without the prior written permission of
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* Broadcom Corporation.
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*
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* 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
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* WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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* PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
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* SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
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* PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
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* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
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* TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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********************************************************************* */
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#ifndef _MII_H_
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#define _MII_H_
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/* Access/command codes */
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#define MII_COMMAND_START 0x01
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#define MII_COMMAND_READ 0x02
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#define MII_COMMAND_WRITE 0x01
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#define MII_COMMAND_ACK 0x02
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/* Registers */
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#define MII_BMCR 0x00 /* Basic Mode Control (rw) */
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#define MII_BMSR 0x01 /* Basic Mode Status (ro) */
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#define MII_PHYIDR1 0x02
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#define MII_PHYIDR2 0x03
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#define MII_ANAR 0x04 /* Autonegotiation Advertisement */
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#define MII_ANLPAR 0x05 /* Autonegotiation Link Partner Ability (rw) */
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#define MII_ANER 0x06 /* Autonegotiation Expansion */
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#define MII_K1CTL 0x09 /* 1000baseT control */
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#define MII_K1STSR 0x0A /* 1K Status Register (ro) */
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#define MII_AUXCTL 0x18 /* aux control register */
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#define MII_AUXSTA 0x19 /* aux status register */
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/* Basic Mode Control register (RW) */
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#define BMCR_RESET 0x8000
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#define BMCR_LOOPBACK 0x4000
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#define BMCR_SPEED0 0x2000
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#define BMCR_ANENABLE 0x1000
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#define BMCR_POWERDOWN 0x0800
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#define BMCR_ISOLATE 0x0400
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#define BMCR_RESTARTAN 0x0200
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#define BMCR_DUPLEX 0x0100
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#define BMCR_COLTEST 0x0080
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#define BMCR_SPEED1 0x0040
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#define BMCR_SPEED1000 (BMCR_SPEED1)
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#define BMCR_SPEED100 (BMCR_SPEED0)
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#define BMCR_SPEED10 0
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/* Basic Mode Status register (RO) */
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#define BMSR_100BT4 0x8000
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#define BMSR_100BT_FDX 0x4000
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#define BMSR_100BT_HDX 0x2000
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#define BMSR_10BT_FDX 0x1000
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#define BMSR_10BT_HDX 0x0800
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#define BMSR_100BT2_FDX 0x0400
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#define BMSR_100BT2_HDX 0x0200
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#define BMSR_1000BT_XSR 0x0100
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#define BMSR_PRESUP 0x0040
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#define BMSR_ANCOMPLETE 0x0020
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#define BMSR_REMFAULT 0x0010
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#define BMSR_AUTONEG 0x0008
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#define BMSR_LINKSTAT 0x0004
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#define BMSR_JABDETECT 0x0002
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#define BMSR_EXTCAPAB 0x0001
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/* PHY Identifer registers (RO) */
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#define PHYIDR1 0x2000
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#define PHYIDR2 0x5C60
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/* Autonegotiation Advertisement register (RW) */
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#define ANAR_NP 0x8000
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#define ANAR_RF 0x2000
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#define ANAR_ASYPAUSE 0x0800
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#define ANAR_PAUSE 0x0400
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#define ANAR_T4 0x0200
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#define ANAR_TXFD 0x0100
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#define ANAR_TXHD 0x0080
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#define ANAR_10FD 0x0040
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#define ANAR_10HD 0x0020
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#define ANAR_PSB 0x001F
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#define PSB_802_3 0x0001 /* 802.3 */
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/* Autonegotiation Link Partner Abilities register (RW) */
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#define ANLPAR_NP 0x8000
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#define ANLPAR_ACK 0x4000
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#define ANLPAR_RF 0x2000
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#define ANLPAR_ASYPAUSE 0x0800
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#define ANLPAR_PAUSE 0x0400
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#define ANLPAR_T4 0x0200
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#define ANLPAR_TXFD 0x0100
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#define ANLPAR_TXHD 0x0080
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#define ANLPAR_10FD 0x0040
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#define ANLPAR_10HD 0x0020
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#define ANLPAR_PSB 0x001F
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/* Autonegotiation Expansion register (RO) */
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#define ANER_PDF 0x0010
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#define ANER_LPNPABLE 0x0008
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#define ANER_NPABLE 0x0004
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#define ANER_PAGERX 0x0002
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#define ANER_LPANABLE 0x0001
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#define ANNPTR_NP 0x8000
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#define ANNPTR_MP 0x2000
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#define ANNPTR_ACK2 0x1000
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#define ANNPTR_TOGTX 0x0800
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#define ANNPTR_CODE 0x0008
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#define ANNPRR_NP 0x8000
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#define ANNPRR_MP 0x2000
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#define ANNPRR_ACK3 0x1000
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#define ANNPRR_TOGTX 0x0800
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#define ANNPRR_CODE 0x0008
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#define K1TCR_TESTMODE 0x0000
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#define K1TCR_MSMCE 0x1000
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#define K1TCR_MSCV 0x0800
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#define K1TCR_RPTR 0x0400
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#define K1TCR_1000BT_FDX 0x200
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#define K1TCR_1000BT_HDX 0x100
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#define K1STSR_MSMCFLT 0x8000
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#define K1STSR_MSCFGRES 0x4000
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#define K1STSR_LRSTAT 0x2000
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#define K1STSR_RRSTAT 0x1000
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#define K1STSR_LP1KFD 0x0800
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#define K1STSR_LP1KHD 0x0400
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#define K1STSR_LPASMDIR 0x0200
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#define K1SCR_1KX_FDX 0x8000
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#define K1SCR_1KX_HDX 0x4000
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#define K1SCR_1KT_FDX 0x2000
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#define K1SCR_1KT_HDX 0x1000
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/*---------------------------------------------------------------------*/
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/* Broadcom PHY MII register address */
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/* use when PhyType is BP_ENET_INTERNAL_PHY */
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/*---------------------------------------------------------------------*/
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#define MII_ASR 0x19
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#define MII_INTERRUPT 0x1A
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#define MII_RESERVED_1B 0x1B
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#define MII_BRCM_TEST 0x1F
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/* MII ASR register. */
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#define MII_ASR_DONE(r) ((r & 0x8000) != 0)
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#define MII_ASR_LINK(r) ((r & 0x0004) != 0)
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#define MII_ASR_FDX(r) (((r & 0x0700) == 0x0700) || ((r & 0x0700) == 0x0500) || ((r & 0x0700) == 0x0200))
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#define MII_ASR_1000(r) (((r & 0x0700) == 0x0700) || ((r & 0x0700) == 0x0600))
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#define MII_ASR_100(r) (((r & 0x0700) == 0x0500) || ((r & 0x0700) == 0x0300))
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#define MII_ASR_10(r) (((r & 0x0700) == 0x0200) || ((r & 0x0700) == 0x0100))
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/* Reserved 0x1B register */
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#define MII_RESERVED_1B_ACT_LED 0x0004
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/* Broadcom Test register. */
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#define MII_BRCM_TEST_SHADOW2_ENABLE 0x0004
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/* MII Interrupt register. */
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#define MII_INTR_ENABLE 0x4000
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#define BCM50612_PHYID2 0x5E60
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#define BCM54610_PHYID2 0xBD63
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#define BCM_PHYID_M 0xFFF0
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#define MII_REGISTER_1C 0x1c
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#define MII_1C_WRITE_ENABLE (1 << 15)
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#define MII_1C_SHADOW_REG_SEL_S 10
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#define MII_1C_SHADOW_REG_SEL_M 0x1F
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#define MII_1C_SHADOW_CLK_ALIGN_CTRL 0x3
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#define GTXCLK_DELAY_BYPASS_DISABLE (1 << 9)
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#define MII_1C_SHADOW_LED_CONTROL 0x9
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#define ACT_LINK_LED_ENABLE (1 << 4)
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#define MII_1C_EXTERNAL_CONTROL_1 0xB
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#define LOM_LED_MODE (1 << 2)
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#define RGMII_MODE_SEL_M 0x3
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#define RGMII_MODE_SEL_S 3
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#define RGMII_MODE_3P3V 0x0
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#define RGMII_MODE_2P5V 0x1
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#define RGMII_MODE_1P8V 0x2
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#define PAGE_CONTROL 0x00
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#define PORT_CTRL_PORT 0
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#define PORT_CTRL_PORT_STATUS_S 5
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#define PORT_CTRL_PORT_STATUS_M (7<<PORT_CTRL_PORT_STATUS_S)
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#define PORT_CTRL_NO_STP (0<<PORT_CTRL_PORT_STATUS_S)
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#define PORT_CTRL_PORT_FORWARDING (5<<PORT_CTRL_PORT_STATUS_S)
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#define PORT_CTRL_SWITCH_RESERVE (7<<2)
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#define PORT_CTRL_TX_DISABLE 0x2
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#define PORT_CTRL_RX_DISABLE 0x1
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#define PORT_CTRL_RXTX_DISABLE (PORT_CTRL_TX_DISABLE|PORT_CTRL_RX_DISABLE)
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#define SOFTWARE_RESET_CTRL 0x79
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#define SOFTWARE_RESET (1<<7)
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#define EN_SW_RST (1<<4)
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#define PAGE_SELECT 0xff
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#define PAGE_MANAGEMENT 0x02
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/* Control page registers */
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#define REG_MII_PORT_CONTROL 0x08
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#define REG_SWITCH_MODE 0x0b
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#define REG_CONTROL_MII1_PORT_STATE_OVERRIDE 0x0e
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#define REG_POWER_DOWN_MODE 0x0f
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/* MII Port Control Register, Page 0x00 Address 0x08 */
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#define REG_MII_PORT_CONTROL_RX_UCST_EN 0x10
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#define REG_MII_PORT_CONTROL_RX_MCST_EN 0x08
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#define REG_MII_PORT_CONTROL_RX_BCST_EN 0x04
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/* Switch mode register, Page 0x00 Address 0x0b */
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#define REG_SWITCH_MODE_FRAME_MANAGE_MODE 0x01
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#define REG_SWITCH_MODE_SW_FWDG_EN 0x02
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/* MII1 Port State Override Register Page 0x00 Address 0x0e */
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#define REG_CONTROL_MPSO_MII_SW_OVERRIDE 0x80
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#define REG_CONTROL_MPSO_REVERSE_MII 0x10
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#define REG_CONTROL_MPSO_LP_FLOW_CONTROL 0x08
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#define REG_CONTROL_MPSO_TX_FLOW_CONTROL 0x20
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#define REG_CONTROL_MPSO_RX_FLOW_CONTROL 0x10
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#define REG_CONTROL_MPSO_SPEED100 0x04
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#define REG_CONTROL_MPSO_SPEED1000 0x08
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#define REG_CONTROL_MPSO_FDX 0x02
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#define REG_CONTROL_MPSO_LINKPASS 0x01
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/* Power down mode register Page 0x00 Address 0x0f */
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#define REG_POWER_DOWN_MODE_PORT1_PHY_DISABLE 0x01
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#define REG_POWER_DOWN_MODE_PORT2_PHY_DISABLE 0x02
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#define REG_POWER_DOWN_MODE_PORT3_PHY_DISABLE 0x04
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#define REG_POWER_DOWN_MODE_PORT4_PHY_DISABLE 0x08
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#define REG_POWER_DOWN_MODE_PORT5_PHY_DISABLE 0x10
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/* Switch control register page 0x0 */
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#define REG_SWITCH_CONTROL 0x20
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#define REG_SWITCH_CONTROL_MII_DUMP_FWD_EN 0x1
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/* Device ID register page 0x02 */
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#define REG_DEVICE_ID 0x30
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#define REG_GLOBAL_CONFIG 0x00
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#define REG_BRCM_HDR_CTRL 0x03
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/* Global Configuration Regiater Page 0x02 Address 0x00 */
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#define ENABLE_MII_PORT 0x80
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/* Broadcom Header Control Register Page 0x02 Address 0x03*/
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#define REG_BRCM_HDR_ENABLE 0x01
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/*---------------------------------------------------------------------*/
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/* 5325 Switch SPI Interface */
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/* use when configuration type is BP_ENET_CONFIG_SPI_SSB_x */
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/*---------------------------------------------------------------------*/
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#define BCM5325_SPI_CMD_LEN 1
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#define BCM5325_SPI_ADDR_LEN 1
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#define BCM5325_SPI_PREPENDCNT (BCM5325_SPI_CMD_LEN+BCM5325_SPI_ADDR_LEN)
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/* 5325 SPI Status Register */
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#define BCM5325_SPI_STS 0xfe
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/* 5325 SPI Status Register definition */
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#define BCM5325_SPI_CMD_SPIF 0x80
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#define BCM5325_SPI_CMD_RACK 0x20
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/* 5325 Command Byte definition */
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#define BCM5325_SPI_CMD_READ 0x00 /* bit 0 - Read/Write */
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#define BCM5325_SPI_CMD_WRITE 0x01 /* bit 0 - Read/Write */
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#define BCM5325_SPI_CHIPID_MASK 0x7 /* bit 3:1 - Chip ID */
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#define BCM5325_SPI_CHIPID_SHIFT 1
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#define BCM5325_SPI_CMD_NORMAL 0x60 /* bit 7:4 - Mode */
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#define BCM5325_SPI_CMD_FAST 0x10 /* bit 4 - Mode */
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/*---------------------------------------------------------------------*/
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/* 5325 Switch Pseudo PHY MII Register */
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/* use when configuration type is BP_ENET_CONFIG_MDIO_PSEUDO_PHY */
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/*---------------------------------------------------------------------*/
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#define PSEUDO_PHY_ADDR 0x1e /* Pseduo PHY address */
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/* Pseudo PHY MII registers */
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#define REG_PSEUDO_PHY_MII_REG16 0x10 /* register 16 - Switch Register Set Access Control Register */
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#define REG_PSEUDO_PHY_MII_REG17 0x11 /* register 17 - Switch Register Set Read/Write Control Register */
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#define REG_PSEUDO_PHY_MII_REG24 0x18 /* register 24 - Switch Accesss Register bit 15:0 */
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#define REG_PSEUDO_PHY_MII_REG25 0x19 /* register 25 - Switch Accesss Register bit 31:16 */
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#ifdef EXT_BCM53134
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#define REG_PSEUDO_PHY_MII_REG26 0x1a /* register 26 - Switch Accesss Register bit 47:32 */
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#define REG_PSEUDO_PHY_MII_REG27 0x1b /* register 27 - Switch Accesss Register bit 63:48 */
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#else
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#define REG_PSEUDO_PHY_MII_REG26 0x20 /* register 26 - Switch Accesss Register bit 47:32 */
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#define REG_PSEUDO_PHY_MII_REG27 0x21 /* register 27 - Switch Accesss Register bit 63:48 */
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#endif
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/*Pseudo PHY MII register 16 Switch Register Set Access Control Register */
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#define REG_PPM_REG16_SWITCH_PAGE_NUMBER_SHIFT 8 /* bit 8..15 - switch page number */
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#define REG_PPM_REG16_MDIO_ENABLE 0x01 /* bit 0 - set MDC/MDIO access enable */
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/*Pseudo PHY MII register 17 Switch Register Set Read/Write Control Register */
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#define REG_PPM_REG17_REG_NUMBER_SHIFT 8 /* bit 8..15 - switch register number */
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#define REG_PPM_REG17_OP_DONE 0x00 /* bit 0..1 - no operation */
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#define REG_PPM_REG17_OP_WRITE 0x01 /* bit 0..1 - write operation */
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#define REG_PPM_REG17_OP_READ 0x02 /* bit 0..1 - read operation */
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uint32 mii_read(uint32 uPhyAddr, uint32 uRegAddr);
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void mii_write(uint32 uPhyAddr, uint32 uRegAddr, uint32 data);
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#define K1CTL_REPEATER_DTE 0x400
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#define K1CTL_1000BT_FDX 0x200
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#define K1CTL_1000BT_HDX 0x100
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#endif /* _MII_H_ */
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