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https://github.com/gnuton/asuswrt-merlin.ng.git
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204 lines
7.7 KiB
C
204 lines
7.7 KiB
C
/*
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Copyright 2000-2012 Broadcom Corporation
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<:label-BRCM:2012:DUAL/GPL:standard
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Unless you and Broadcom execute a separate written software license
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agreement governing use of this software, this software is licensed
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to you under the terms of the GNU General Public License version 2
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(the "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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with the following added to such license:
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As a special exception, the copyright holders of this software give
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you permission to link this software with independent modules, and
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to copy and distribute the resulting executable under terms of your
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choice, provided that you also meet, for each linked independent
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module, the terms and conditions of the license of that module.
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An independent module is a module which is not derived from this
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software. The special exception does not apply to any modifications
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of the software.
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Not withstanding the above, under no circumstances may you combine
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this software in any way with any other Broadcom software provided
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under a license other than the GPL, without Broadcom's express prior
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written consent.
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:>
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*/
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#ifndef __ROBOSW_REG_H
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#define __ROBOSW_REG_H
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/*
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Caution:
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The parameters defined in this file are only used by bcm_ethsw_impl2.c switch
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basic initialization code as well as CFE initialization code.
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It is not defined for Linux environment code since CFE/SwInit has different
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port numbering and structure definition from Linux code but using the same
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Macro names.
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Don't include this head file in any Linux code other than bcm_ethsw_impl2.c.
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If you need to expand shared parameters for robo switch, add them into
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robosw_reg_shared.h instead.
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*/
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#include "robosw_reg_shared.h"
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// These macros make offset validation vs. data sheet easier.
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#define group(type, name, start_offset, next) type name[(next - start_offset) / sizeof(type)]
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#define entry(type, name, start_offset, next) type name
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typedef struct RoboSwitch {
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group(byte, PortCtrl, 0x0000, 0x0009);
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group(byte, Reserved0009, 0x0009, 0x000b);
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entry(byte, SwitchMode, 0x000b, 0x000c);
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entry(uint16, PauseQuanta, 0x000c, 0x000e);
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entry(byte, ImpOverride, 0x000e, 0x000f);
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entry(byte, LedRefresh, 0x000f, 0x0010);
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entry(uint16, LedFunc0, 0x0010, 0x0012);
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entry(uint16, LedFunc1, 0x0012, 0x0014);
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entry(uint16, LedFuncMap, 0x0014, 0x0016);
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entry(uint16, LedEnableMap, 0x0016, 0x0018);
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entry(uint16, LedMap0, 0x0018, 0x001a);
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entry(uint16, LedMap1, 0x001a, 0x001c);
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group(byte, Reserved001c, 0x001c, 0x0020);
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group(byte, Reserved0020, 0x0020, 0x0021);
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entry(byte, ForwardCtrl, 0x0021, 0x0022);
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group(byte, Reserved0022, 0x0022, 0x0024);
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entry(uint16, ProtSelect, 0x0024, 0x0026);
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entry(uint16, WanSelect, 0x0026, 0x0028);
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entry(uint32, PauseCap, 0x0028, 0x002c);
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group(byte, Reserved002c, 0x002c, 0x002f);
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entry(byte, MultiCtrl, 0x002f, 0x0030);
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group(byte, Reserved0030, 0x0030, 0x0031);
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entry(byte, TxqFlush, 0x0031, 0x0032);
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entry(uint16, UniFail, 0x0032, 0x0034);
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entry(uint16, MultiFail, 0x0034, 0x0036);
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entry(uint16, MlfIpmc, 0x0036, 0x0038);
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entry(uint16, PausePassRx, 0x0038, 0x003a);
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entry(uint16, PausePassTx, 0x003a, 0x003c);
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entry(uint16, DisableLearn, 0x003c, 0x003e);
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group(byte, Reserved003e, 0x003e, 0x004a);
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entry(uint16, PllTest, 0x004a, 0x004c);
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group(byte, Reserved004c, 0x004c, 0x0058);
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group(byte, PortOverride, 0x0058, 0x0060);
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group(byte, Reserved0061, 0x0060, 0x0064);
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entry(byte, ImpRgmiiCtrlP4, 0x0064, 0x0065);
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entry(byte, ImpRgmiiCtrlP5, 0x0065, 0x0066);
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entry(byte, ImpRgmiiCtrlP6, 0x0066, 0x0067);
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entry(byte, ImpRgmiiCtrlP7, 0x0067, 0x0068);
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group(byte, Reserved0068, 0x0068, 0x006c);
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entry(byte, ImpRgmiiTimingDelayP4, 0x006c, 0x006d);
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entry(byte, ImpRgmiiTimingDelayP5, 0x006d, 0x006e);
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entry(byte, ImpRgmiiTimingDelayP6, 0x006e, 0x006f);
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entry(byte, ImpRgmiiTimingDelayP7, 0x006f, 0x0070);
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group(byte, Reserved0070, 0x0070, 0x0079);
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entry(byte, SWResetCtrl, 0x0079, 0x007a);
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group(byte, Reserved007a, 0x007a, 0x0090);
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entry(uint32, Rxfilt_Ctl, 0x0090, 0x0094);
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entry(uint32, Cmf_En_Ctl, 0x0094, 0x0098);
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group(byte, Reserved0098, 0x0098, 0x00a0);
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entry(uint32, SwpktCtrl0, 0x00a0, 0x00a4);
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entry(uint32, SwpktCtrl1, 0x00a4, 0x00a8);
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group(byte, Reserved00a8, 0x00a8, 0x00b0);
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entry(uint32, MdioCtrl, 0x00b0, 0x00b4);
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entry(uint16, MdioData, 0x00b4, 0x00b6);
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group(byte, Reserved00b4, 0x00b6, 0x0200);
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entry(byte, GlbMgmt, 0x0200, 0x0201);
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entry(byte, ChpBoxID, 0x0201, 0x0202);
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entry(byte, MngPID, 0x0202, 0x0203);
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group(byte, Reserved0203, 0x0203, 0x1100);
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entry(uint16, MIICtrl0, 0x1100, 0x1101);
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} RoboSwitch;
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#define SWITCH ((volatile RoboSwitch * const)SWITCH_BASE)
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#define PAGE_PBVLAN 0x31
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#define PBVLAN_OFFSET (PAGE_PBVLAN << 8)
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#define PBMAP_MIPS 0x100
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#define SWITCH_PBVLAN ((volatile uint16 * const)(SWITCH_BASE + PBVLAN_OFFSET))
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#define PortCtrl_Forwarding 0xa0
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#define PortCtrl_Learning 0x80
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#define PortCtrl_Listening 0x60
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#define PortCtrl_Blocking 0x40
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#define PortCtrl_Disable 0x20
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#define PortCtrl_RxUcstEn 0x10
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#define PortCtrl_RxMcstEn 0x08
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#define PortCtrl_RxBcstEn 0x04
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#define PortCtrl_DisableTx 0x02
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#define PortCtrl_DisableRx 0x01
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#define SwitchMode_FwdgEn 0x02
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#define SwitchMode_ManageMode 0x01
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#define ImpOverride_Force 0x80
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#define ImpOverride_TxFlow 0x20
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#define ImpOverrode_RxFlow 0x10
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#define ImpOverride_1000Mbs 0x08
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#define ImpOverride_100Mbs 0x04
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#define ImpOverride_10Mbs 0x00
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#define ImpOverride_Fdx 0x02
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#define ImpOverride_Linkup 0x01
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#define PortOverride_Enable 0x40
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#define PortOverride_TxFlow 0x20
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#define PortOverride_RxFlow 0x10
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#define PortOverride_1000Mbs 0x08
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#define PortOverride_100Mbs 0x04
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#define PortOverride_10Mbs 0x00
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#define PortOverride_Fdx 0x02
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#define PortOverride_Linkup 0x01
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#define GlbMgmt_EnableImp 0x80
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#define GlbMgmt_IgmpSnooping 0x08
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#define GlbMgmt_ReceiveBpdu 0x02
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#define GlbMgmt_ResetMib 0x01
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#define MdioCtrl_Write (1 << 31)
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#define MdioCtrl_Read (1 << 30)
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#define MdioCtrl_Ext (1 << 16)
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#define MdioCtrl_ID_Shift 25
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#define MdioCtrl_ID_Mask (0x1f << MdioCtrl_ID_Shift)
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#define MdioCtrl_Addr_Shift 20
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#define MdioCtrl_Addr_Mask (0x1f << MdioCtrl_Addr_Shift)
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#define ImpRgmiiCtrl_GMII_En 0x80
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#define ImpRgmiiCtrl_Force_RGMII 0x40
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#define ImpRgmiiCtrl_Mode_RGMII 0x00
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#define ImpRgmiiCtrl_Mode_RvMII 0x20
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#define ImpRgmiiCtrl_Mode_MII 0x10
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#define ImpRgmiiCtrl_Mode_GMII 0x30
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#define ImpRgmiiCtrl_Mode_Mask 0x30
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#define ImpRgmiiCtrl_DLL_IDDQ 0x04
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#define ImpRgmiiCtrl_DLL_RXC_Bypass 0x02
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#define ImpRgmiiCtrl_Timing_Sel 0x01
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#define ImpRgmiiTimingDelayDefault 0xF9
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#define PORT_4_PORT_ID 4
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#define PORT_5_PORT_ID 5
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#define PORT_6_PORT_ID 6
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#define PORT_7_PORT_ID 7
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#if defined (_BCM963268_) || defined(CONFIG_BCM963268)
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#define EPHY_PORTS 8
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#define GPHY_PORT_ID 3
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#endif
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#if defined (_BCM963381_) || defined(CONFIG_BCM963381)
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#define EPHY_PORTS 8
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#define GPHY_PORT_ID 3
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#endif
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void ethsw_rreg_ext(int access_type, int page, int reg, uint8 *data, int len);
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void ethsw_wreg_ext(int access_type, int page, int reg, uint8 *data, int len);
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/* definitions for access_type */
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#define MDIO_BUS 0
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#define SPI_BUS 1
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void robosw_check_ports(void);
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#endif
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