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lazygit/vendor/github.com/pjbgf/sha1cd/ubc/ubc_amd64.s
Stefan Haller 4cf49ff449 Bump go-git
2025-04-09 11:23:55 +02:00

1897 lines
43 KiB
ArmAsm
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// Code generated by command: go run asm.go -out ../ubc_amd64.s -pkg ubc. DO NOT EDIT.
//go:build !noasm && gc && amd64
#include "textflag.h"
// func CalculateDvMaskAMD64(W [80]uint32) uint32
TEXT ·CalculateDvMaskAMD64(SB), NOSPLIT, $0-324
MOVL $0xffffffff, AX
// (((((W[44] ^ W[45]) >> 29) & 1) - 1) | ^(DV_I_48_0_bit | DV_I_51_0_bit | DV_I_52_0_bit | DV_II_45_0_bit | DV_II_46_0_bit | DV_II_50_0_bit | DV_II_51_0_bit))
MOVL W_44+176(FP), CX
MOVL W_45+180(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xfd7c5f7f, CX
ANDL CX, AX
// mask &= (((((W[49] ^ W[50]) >> 29) & 1) - 1) | ^(DV_I_46_0_bit | DV_II_45_0_bit | DV_II_50_0_bit | DV_II_51_0_bit | DV_II_55_0_bit | DV_II_56_0_bit))
MOVL W_49+196(FP), CX
MOVL W_50+200(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x3d7efff7, CX
ANDL CX, AX
// mask &= (((((W[48] ^ W[49]) >> 29) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_52_0_bit | DV_II_49_0_bit | DV_II_50_0_bit | DV_II_54_0_bit | DV_II_55_0_bit))
MOVL W_48+192(FP), CX
MOVL W_49+196(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x9f5f7ffb, CX
ANDL CX, AX
// mask &= ((((W[47] ^ (W[50] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_51_0_bit | DV_II_56_0_bit))
MOVL W_47+188(FP), CX
MOVL W_50+200(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0x7dfedddf, CX
ANDL CX, AX
// mask &= (((((W[47] ^ W[48]) >> 29) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_51_0_bit | DV_II_48_0_bit | DV_II_49_0_bit | DV_II_53_0_bit | DV_II_54_0_bit))
MOVL W_47+188(FP), CX
MOVL W_48+192(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xcfcfdffd, CX
ANDL CX, AX
// mask &= (((((W[46] >> 4) ^ (W[49] >> 29)) & 1) - 1) | ^(DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit | DV_II_50_0_bit | DV_II_55_0_bit))
MOVL W_46+184(FP), CX
SHRL $0x04, CX
MOVL W_49+196(FP), DX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xbf7f7777, CX
ANDL CX, AX
// mask &= (((((W[46] ^ W[47]) >> 29) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_50_0_bit | DV_II_47_0_bit | DV_II_48_0_bit | DV_II_52_0_bit | DV_II_53_0_bit))
MOVL W_46+184(FP), CX
MOVL W_47+188(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xe7e7f7fe, CX
ANDL CX, AX
// mask &= (((((W[45] >> 4) ^ (W[48] >> 29)) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit | DV_II_49_0_bit | DV_II_54_0_bit))
MOVL W_45+180(FP), CX
SHRL $0x04, CX
MOVL W_48+192(FP), DX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xdfdfdddb, CX
ANDL CX, AX
// mask &= (((((W[45] ^ W[46]) >> 29) & 1) - 1) | ^(DV_I_49_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_47_0_bit | DV_II_51_0_bit | DV_II_52_0_bit))
MOVL W_45+180(FP), CX
MOVL W_46+184(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xf5f57dff, CX
ANDL CX, AX
// mask &= (((((W[44] >> 4) ^ (W[47] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit | DV_II_48_0_bit | DV_II_53_0_bit))
MOVL W_44+176(FP), CX
SHRL $0x04, CX
MOVL W_47+188(FP), DX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xefeff775, CX
ANDL CX, AX
// mask &= (((((W[43] >> 4) ^ (W[46] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit | DV_II_47_0_bit | DV_II_52_0_bit))
MOVL W_43+172(FP), CX
SHRL $0x04, CX
MOVL W_46+184(FP), DX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xf7f7fdda, CX
ANDL CX, AX
// mask &= (((((W[43] ^ W[44]) >> 29) & 1) - 1) | ^(DV_I_47_0_bit | DV_I_50_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_49_0_bit | DV_II_50_0_bit))
MOVL W_43+172(FP), CX
MOVL W_44+176(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xff5ed7df, CX
ANDL CX, AX
// mask &= (((((W[42] >> 4) ^ (W[45] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_51_0_bit))
MOVL W_42+168(FP), CX
SHRL $0x04, CX
MOVL W_45+180(FP), DX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xfdfd7f75, CX
ANDL CX, AX
// mask &= (((((W[41] >> 4) ^ (W[44] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_50_0_bit))
MOVL W_41+164(FP), CX
SHRL $0x04, CX
MOVL W_44+176(FP), DX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xff7edfda, CX
ANDL CX, AX
// mask &= (((((W[40] ^ W[41]) >> 29) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_47_0_bit | DV_I_48_0_bit | DV_II_46_0_bit | DV_II_47_0_bit | DV_II_56_0_bit))
MOVL W_40+160(FP), CX
MOVL W_41+164(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x7ff5ff5d, CX
ANDL CX, AX
// mask &= (((((W[54] ^ W[55]) >> 29) & 1) - 1) | ^(DV_I_51_0_bit | DV_II_47_0_bit | DV_II_50_0_bit | DV_II_55_0_bit | DV_II_56_0_bit))
MOVL W_54+216(FP), CX
MOVL W_55+220(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x3f77dfff, CX
ANDL CX, AX
// mask &= (((((W[53] ^ W[54]) >> 29) & 1) - 1) | ^(DV_I_50_0_bit | DV_II_46_0_bit | DV_II_49_0_bit | DV_II_54_0_bit | DV_II_55_0_bit))
MOVL W_53+212(FP), CX
MOVL W_54+216(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x9fddf7ff, CX
ANDL CX, AX
// mask &= (((((W[52] ^ W[53]) >> 29) & 1) - 1) | ^(DV_I_49_0_bit | DV_II_45_0_bit | DV_II_48_0_bit | DV_II_53_0_bit | DV_II_54_0_bit))
MOVL W_52+208(FP), CX
MOVL W_53+212(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xcfeefdff, CX
ANDL CX, AX
// mask &= ((((W[50] ^ (W[53] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_50_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_48_0_bit | DV_II_54_0_bit))
MOVL W_50+200(FP), CX
MOVL W_53+212(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xdfed77ff, CX
ANDL CX, AX
// mask &= (((((W[50] ^ W[51]) >> 29) & 1) - 1) | ^(DV_I_47_0_bit | DV_II_46_0_bit | DV_II_51_0_bit | DV_II_52_0_bit | DV_II_56_0_bit))
MOVL W_50+200(FP), CX
MOVL W_51+204(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x75fdffdf, CX
ANDL CX, AX
// mask &= ((((W[49] ^ (W[52] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit | DV_II_47_0_bit | DV_II_53_0_bit))
MOVL W_49+196(FP), CX
MOVL W_52+208(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xeff6ddff, CX
ANDL CX, AX
// mask &= ((((W[48] ^ (W[51] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit | DV_II_46_0_bit | DV_II_52_0_bit))
MOVL W_48+192(FP), CX
MOVL W_51+204(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xf7fd777f, CX
ANDL CX, AX
// mask &= (((((W[42] ^ W[43]) >> 29) & 1) - 1) | ^(DV_I_46_0_bit | DV_I_49_0_bit | DV_I_50_0_bit | DV_II_48_0_bit | DV_II_49_0_bit))
MOVL W_42+168(FP), CX
MOVL W_43+172(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xffcff5f7, CX
ANDL CX, AX
// mask &= (((((W[41] ^ W[42]) >> 29) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_48_0_bit | DV_I_49_0_bit | DV_II_47_0_bit | DV_II_48_0_bit))
MOVL W_41+164(FP), CX
MOVL W_42+168(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xffe7fd7b, CX
ANDL CX, AX
// mask &= (((((W[40] >> 4) ^ (W[43] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_50_0_bit | DV_II_49_0_bit | DV_II_56_0_bit))
MOVL W_40+160(FP), CX
MOVL W_43+172(FP), DX
SHRL $0x04, CX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x7fdff7f5, CX
ANDL CX, AX
// mask &= (((((W[39] >> 4) ^ (W[42] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_49_0_bit | DV_II_48_0_bit | DV_II_55_0_bit))
MOVL W_39+156(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x04, CX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xbfeffdfa, CX
ANDL CX, AX
// if (mask & (DV_I_44_0_bit | DV_I_48_0_bit | DV_II_47_0_bit | DV_II_54_0_bit | DV_II_56_0_bit)) != 0 {
// mask &= (((((W[38] >> 4) ^ (W[41] >> 29)) & 1) - 1) | ^(DV_I_44_0_bit | DV_I_48_0_bit | DV_II_47_0_bit | DV_II_54_0_bit | DV_II_56_0_bit))
// }
TESTL $0xa0080082, AX
JE f1
MOVL W_38+152(FP), CX
MOVL W_41+164(FP), DX
SHRL $0x04, CX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x5ff7ff7d, CX
ANDL CX, AX
f1:
// mask &= (((((W[37] >> 4) ^ (W[40] >> 29)) & 1) - 1) | ^(DV_I_43_0_bit | DV_I_47_0_bit | DV_II_46_0_bit | DV_II_53_0_bit | DV_II_55_0_bit))
MOVL W_37+148(FP), CX
MOVL W_40+160(FP), DX
SHRL $0x04, CX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xaffdffde, CX
ANDL CX, AX
// if (mask & (DV_I_52_0_bit | DV_II_48_0_bit | DV_II_51_0_bit | DV_II_56_0_bit)) != 0 {
// mask &= (((((W[55] ^ W[56]) >> 29) & 1) - 1) | ^(DV_I_52_0_bit | DV_II_48_0_bit | DV_II_51_0_bit | DV_II_56_0_bit))
// }
TESTL $0x82108000, AX
JE f2
MOVL W_55+220(FP), CX
MOVL W_56+224(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0x7def7fff, CX
ANDL CX, AX
f2:
// if (mask & (DV_I_52_0_bit | DV_II_48_0_bit | DV_II_50_0_bit | DV_II_56_0_bit)) != 0 {
// mask &= ((((W[52] ^ (W[55] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_52_0_bit | DV_II_48_0_bit | DV_II_50_0_bit | DV_II_56_0_bit))
// }
TESTL $0x80908000, AX
JE f3
MOVL W_52+208(FP), CX
MOVL W_55+220(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0x7f6f7fff, CX
ANDL CX, AX
f3:
// if (mask & (DV_I_51_0_bit | DV_II_47_0_bit | DV_II_49_0_bit | DV_II_55_0_bit)) != 0 {
// mask &= ((((W[51] ^ (W[54] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_51_0_bit | DV_II_47_0_bit | DV_II_49_0_bit | DV_II_55_0_bit))
// }
TESTL $0x40282000, AX
JE f4
MOVL W_51+204(FP), CX
MOVL W_54+216(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xbfd7dfff, CX
ANDL CX, AX
f4:
// if (mask & (DV_I_48_0_bit | DV_II_47_0_bit | DV_II_52_0_bit | DV_II_53_0_bit)) != 0 {
// mask &= (((((W[51] ^ W[52]) >> 29) & 1) - 1) | ^(DV_I_48_0_bit | DV_II_47_0_bit | DV_II_52_0_bit | DV_II_53_0_bit))
// }
TESTL $0x18080080, AX
JE f5
MOVL W_51+204(FP), CX
MOVL W_52+208(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xe7f7ff7f, CX
ANDL CX, AX
f5:
// if (mask & (DV_I_46_0_bit | DV_I_49_0_bit | DV_II_45_0_bit | DV_II_48_0_bit)) != 0 {
// mask &= (((((W[36] >> 4) ^ (W[40] >> 29)) & 1) - 1) | ^(DV_I_46_0_bit | DV_I_49_0_bit | DV_II_45_0_bit | DV_II_48_0_bit))
// }
TESTL $0x00110208, AX
JE f6
MOVL W_36+144(FP), CX
SHRL $0x04, CX
MOVL W_40+160(FP), DX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xffeefdf7, CX
ANDL CX, AX
f6:
// if (mask & (DV_I_52_0_bit | DV_II_48_0_bit | DV_II_49_0_bit)) != 0 {
// mask &= ((0 - (((W[53] ^ W[56]) >> 29) & 1)) | ^(DV_I_52_0_bit | DV_II_48_0_bit | DV_II_49_0_bit))
// }
TESTL $0x00308000, AX
JE f7
MOVL W_53+212(FP), CX
MOVL W_56+224(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xffcf7fff, CX
ANDL CX, AX
f7:
// if (mask & (DV_I_50_0_bit | DV_II_46_0_bit | DV_II_47_0_bit)) != 0 {
// mask &= ((0 - (((W[51] ^ W[54]) >> 29) & 1)) | ^(DV_I_50_0_bit | DV_II_46_0_bit | DV_II_47_0_bit))
// }
TESTL $0x000a0800, AX
JE f8
MOVL W_51+204(FP), CX
MOVL W_54+216(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xfff5f7ff, CX
ANDL CX, AX
f8:
// if (mask & (DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit)) != 0 {
// mask &= ((0 - (((W[50] ^ W[52]) >> 29) & 1)) | ^(DV_I_49_0_bit | DV_I_51_0_bit | DV_II_45_0_bit))
// }
TESTL $0x00012200, AX
JE f9
MOVL W_50+200(FP), CX
MOVL W_52+208(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xfffeddff, CX
ANDL CX, AX
f9:
// if (mask & (DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit)) != 0 {
// mask &= ((0 - (((W[49] ^ W[51]) >> 29) & 1)) | ^(DV_I_48_0_bit | DV_I_50_0_bit | DV_I_52_0_bit))
// }
TESTL $0x00008880, AX
JE f10
MOVL W_49+196(FP), CX
MOVL W_51+204(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xffff777f, CX
ANDL CX, AX
f10:
// if (mask & (DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit)) != 0 {
// mask &= ((0 - (((W[48] ^ W[50]) >> 29) & 1)) | ^(DV_I_47_0_bit | DV_I_49_0_bit | DV_I_51_0_bit))
// }
TESTL $0x00002220, AX
JE f11
MOVL W_48+192(FP), CX
MOVL W_50+200(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xffffdddf, CX
ANDL CX, AX
f11:
// if (mask & (DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit)) != 0 {
// mask &= ((0 - (((W[47] ^ W[49]) >> 29) & 1)) | ^(DV_I_46_0_bit | DV_I_48_0_bit | DV_I_50_0_bit))
// }
TESTL $0x00000888, AX
JE f12
MOVL W_47+188(FP), CX
MOVL W_49+196(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xfffff777, CX
ANDL CX, AX
f12:
// if (mask & (DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit)) != 0 {
// mask &= ((0 - (((W[46] ^ W[48]) >> 29) & 1)) | ^(DV_I_45_0_bit | DV_I_47_0_bit | DV_I_49_0_bit))
// }
TESTL $0x00000224, AX
JE f13
MOVL W_46+184(FP), CX
MOVL W_48+192(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xfffffddb, CX
ANDL CX, AX
f13:
// mask &= ((((W[45] ^ W[47]) & (1 << 6)) - (1 << 6)) | ^(DV_I_47_2_bit | DV_I_49_2_bit | DV_I_51_2_bit))
MOVL W_45+180(FP), CX
MOVL W_47+188(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
SUBL $0x00000040, CX
ORL $0xffffbbbf, CX
ANDL CX, AX
// if (mask & (DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit)) != 0 {
// mask &= ((0 - (((W[45] ^ W[47]) >> 29) & 1)) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_I_48_0_bit))
// }
TESTL $0x0000008a, AX
JE f14
MOVL W_45+180(FP), CX
MOVL W_47+188(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xffffff75, CX
ANDL CX, AX
f14:
// mask &= (((((W[44] ^ W[46]) >> 6) & 1) - 1) | ^(DV_I_46_2_bit | DV_I_48_2_bit | DV_I_50_2_bit))
MOVL W_44+176(FP), CX
MOVL W_46+184(FP), DX
XORL DX, CX
SHRL $0x06, CX
ANDL $0x00000001, CX
DECL CX
ORL $0xffffeeef, CX
ANDL CX, AX
// if (mask & (DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit)) != 0 {
// mask &= ((0 - (((W[44] ^ W[46]) >> 29) & 1)) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_I_47_0_bit))
// }
TESTL $0x00000025, AX
JE f15
MOVL W_44+176(FP), CX
MOVL W_46+184(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xffffffda, CX
ANDL CX, AX
f15:
// mask &= ((0 - ((W[41] ^ (W[42] >> 5)) & (1 << 1))) | ^(DV_I_48_2_bit | DV_II_46_2_bit | DV_II_51_2_bit))
MOVL W_41+164(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xfbfbfeff, CX
ANDL CX, AX
// mask &= ((0 - ((W[40] ^ (W[41] >> 5)) & (1 << 1))) | ^(DV_I_47_2_bit | DV_I_51_2_bit | DV_II_50_2_bit))
MOVL W_40+160(FP), CX
MOVL W_41+164(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xfeffbfbf, CX
ANDL CX, AX
// if (mask & (DV_I_44_0_bit | DV_I_46_0_bit | DV_II_56_0_bit)) != 0 {
// mask &= ((0 - (((W[40] ^ W[42]) >> 4) & 1)) | ^(DV_I_44_0_bit | DV_I_46_0_bit | DV_II_56_0_bit))
// }
TESTL $0x8000000a, AX
JE f16
MOVL W_40+160(FP), CX
MOVL W_42+168(FP), DX
XORL DX, CX
SHRL $0x04, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0x7ffffff5, CX
ANDL CX, AX
f16:
// mask &= ((0 - ((W[39] ^ (W[40] >> 5)) & (1 << 1))) | ^(DV_I_46_2_bit | DV_I_50_2_bit | DV_II_49_2_bit))
MOVL W_39+156(FP), CX
MOVL W_40+160(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xffbfefef, CX
ANDL CX, AX
// if (mask & (DV_I_43_0_bit | DV_I_45_0_bit | DV_II_55_0_bit)) != 0 {
// mask &= ((0 - (((W[39] ^ W[41]) >> 4) & 1)) | ^(DV_I_43_0_bit | DV_I_45_0_bit | DV_II_55_0_bit))
// }
TESTL $0x40000005, AX
JE f17
MOVL W_39+156(FP), CX
MOVL W_41+164(FP), DX
XORL DX, CX
SHRL $0x04, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xbffffffa, CX
ANDL CX, AX
f17:
// if (mask & (DV_I_44_0_bit | DV_II_54_0_bit | DV_II_56_0_bit)) != 0 {
// mask &= ((0 - (((W[38] ^ W[40]) >> 4) & 1)) | ^(DV_I_44_0_bit | DV_II_54_0_bit | DV_II_56_0_bit))
// }
TESTL $0xa0000002, AX
JE f18
MOVL W_38+152(FP), CX
MOVL W_40+160(FP), DX
XORL DX, CX
SHRL $0x04, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0x5ffffffd, CX
ANDL CX, AX
f18:
// if (mask & (DV_I_43_0_bit | DV_II_53_0_bit | DV_II_55_0_bit)) != 0 {
// mask &= ((0 - (((W[37] ^ W[39]) >> 4) & 1)) | ^(DV_I_43_0_bit | DV_II_53_0_bit | DV_II_55_0_bit))
// }
TESTL $0x50000001, AX
JE f19
MOVL W_37+148(FP), CX
MOVL W_39+156(FP), DX
XORL DX, CX
SHRL $0x04, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xaffffffe, CX
ANDL CX, AX
f19:
// mask &= ((0 - ((W[36] ^ (W[37] >> 5)) & (1 << 1))) | ^(DV_I_47_2_bit | DV_I_50_2_bit | DV_II_46_2_bit))
MOVL W_36+144(FP), CX
MOVL W_37+148(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xfffbefbf, CX
ANDL CX, AX
// if (mask & (DV_I_45_0_bit | DV_I_48_0_bit | DV_II_47_0_bit)) != 0 {
// mask &= (((((W[35] >> 4) ^ (W[39] >> 29)) & 1) - 1) | ^(DV_I_45_0_bit | DV_I_48_0_bit | DV_II_47_0_bit))
// }
TESTL $0x00080084, AX
JE f20
MOVL W_35+140(FP), CX
MOVL W_39+156(FP), DX
SHRL $0x04, CX
SHRL $0x1d, DX
XORL DX, CX
ANDL $0x00000001, CX
SUBL $0x00000001, CX
ORL $0xfff7ff7b, CX
ANDL CX, AX
f20:
// if (mask & (DV_I_48_0_bit | DV_II_48_0_bit)) != 0 {
// mask &= ((0 - ((W[63] ^ (W[64] >> 5)) & (1 << 0))) | ^(DV_I_48_0_bit | DV_II_48_0_bit))
// }
TESTL $0x00100080, AX
JE f21
MOVL W_63+252(FP), CX
MOVL W_64+256(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xffefff7f, CX
ANDL CX, AX
f21:
// if (mask & (DV_I_45_0_bit | DV_II_45_0_bit)) != 0 {
// mask &= ((0 - ((W[63] ^ (W[64] >> 5)) & (1 << 1))) | ^(DV_I_45_0_bit | DV_II_45_0_bit))
// }
TESTL $0x00010004, AX
JE f22
MOVL W_63+252(FP), CX
MOVL W_64+256(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xfffefffb, CX
ANDL CX, AX
f22:
// if (mask & (DV_I_47_0_bit | DV_II_47_0_bit)) != 0 {
// mask &= ((0 - ((W[62] ^ (W[63] >> 5)) & (1 << 0))) | ^(DV_I_47_0_bit | DV_II_47_0_bit))
// }
TESTL $0x00080020, AX
JE f23
MOVL W_62+248(FP), CX
MOVL W_63+252(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xfff7ffdf, CX
ANDL CX, AX
f23:
// if (mask & (DV_I_46_0_bit | DV_II_46_0_bit)) != 0 {
// mask &= ((0 - ((W[61] ^ (W[62] >> 5)) & (1 << 0))) | ^(DV_I_46_0_bit | DV_II_46_0_bit))
// }
TESTL $0x00020008, AX
JE f24
MOVL W_61+244(FP), CX
MOVL W_62+248(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xfffdfff7, CX
ANDL CX, AX
f24:
// mask &= ((0 - ((W[61] ^ (W[62] >> 5)) & (1 << 2))) | ^(DV_I_46_2_bit | DV_II_46_2_bit))
MOVL W_61+244(FP), CX
MOVL W_62+248(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000004, CX
NEGL CX
ORL $0xfffbffef, CX
ANDL CX, AX
// if (mask & (DV_I_45_0_bit | DV_II_45_0_bit)) != 0 {
// mask &= ((0 - ((W[60] ^ (W[61] >> 5)) & (1 << 0))) | ^(DV_I_45_0_bit | DV_II_45_0_bit))
// }
TESTL $0x00010004, AX
JE f25
MOVL W_60+240(FP), CX
MOVL W_61+244(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xfffefffb, CX
ANDL CX, AX
f25:
// if (mask & (DV_II_51_0_bit | DV_II_54_0_bit)) != 0 {
// mask &= (((((W[58] ^ W[59]) >> 29) & 1) - 1) | ^(DV_II_51_0_bit | DV_II_54_0_bit))
// }
TESTL $0x22000000, AX
JE f26
MOVL W_58+232(FP), CX
MOVL W_59+236(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
SUBL $0x00000001, CX
ORL $0xddffffff, CX
ANDL CX, AX
f26:
// if (mask & (DV_II_50_0_bit | DV_II_53_0_bit)) != 0 {
// mask &= (((((W[57] ^ W[58]) >> 29) & 1) - 1) | ^(DV_II_50_0_bit | DV_II_53_0_bit))
// }
TESTL $0x10800000, AX
JE f27
MOVL W_57+228(FP), CX
MOVL W_58+232(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
SUBL $0x00000001, CX
ORL $0xef7fffff, CX
ANDL CX, AX
f27:
// if (mask & (DV_II_52_0_bit | DV_II_54_0_bit)) != 0 {
// mask &= ((((W[56] ^ (W[59] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_52_0_bit | DV_II_54_0_bit))
// }
TESTL $0x28000000, AX
JE f28
MOVL W_56+224(FP), CX
MOVL W_59+236(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xd7ffffff, CX
ANDL CX, AX
f28:
// if (mask & (DV_II_51_0_bit | DV_II_52_0_bit)) != 0 {
// mask &= ((0 - (((W[56] ^ W[59]) >> 29) & 1)) | ^(DV_II_51_0_bit | DV_II_52_0_bit))
// }
TESTL $0x0a000000, AX
JE f29
MOVL W_56+224(FP), CX
MOVL W_59+236(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xf5ffffff, CX
ANDL CX, AX
f29:
// if (mask & (DV_II_49_0_bit | DV_II_52_0_bit)) != 0 {
// mask &= (((((W[56] ^ W[57]) >> 29) & 1) - 1) | ^(DV_II_49_0_bit | DV_II_52_0_bit))
// }
TESTL $0x08200000, AX
JE f30
MOVL W_56+224(FP), CX
MOVL W_57+228(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
SUBL $0x00000001, CX
ORL $0xf7dfffff, CX
ANDL CX, AX
f30:
// if (mask & (DV_II_51_0_bit | DV_II_53_0_bit)) != 0 {
// mask &= ((((W[55] ^ (W[58] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_51_0_bit | DV_II_53_0_bit))
// }
TESTL $0x12000000, AX
JE f31
MOVL W_55+220(FP), CX
MOVL W_58+232(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xedffffff, CX
ANDL CX, AX
f31:
// if (mask & (DV_II_50_0_bit | DV_II_52_0_bit)) != 0 {
// mask &= ((((W[54] ^ (W[57] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_50_0_bit | DV_II_52_0_bit))
// }
TESTL $0x08800000, AX
JE f32
MOVL W_54+216(FP), CX
MOVL W_57+228(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xf77fffff, CX
ANDL CX, AX
f32:
// if (mask & (DV_II_49_0_bit | DV_II_51_0_bit)) != 0 {
// mask &= ((((W[53] ^ (W[56] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_II_49_0_bit | DV_II_51_0_bit))
// }
TESTL $0x02200000, AX
JE f33
MOVL W_53+212(FP), CX
MOVL W_56+224(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xfddfffff, CX
ANDL CX, AX
f33:
// mask &= ((((W[51] ^ (W[50] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_50_2_bit | DV_II_46_2_bit))
MOVL W_51+204(FP), CX
MOVL W_50+200(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
SUBL $0x00000002, CX
ORL $0xfffbefff, CX
ANDL CX, AX
// mask &= ((((W[48] ^ W[50]) & (1 << 6)) - (1 << 6)) | ^(DV_I_50_2_bit | DV_II_46_2_bit))
MOVL W_48+192(FP), CX
MOVL W_50+200(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
SUBL $0x00000040, CX
ORL $0xfffbefff, CX
ANDL CX, AX
// if (mask & (DV_I_51_0_bit | DV_I_52_0_bit)) != 0 {
// mask &= ((0 - (((W[48] ^ W[55]) >> 29) & 1)) | ^(DV_I_51_0_bit | DV_I_52_0_bit))
// }
TESTL $0x0000a000, AX
JE f34
MOVL W_48+192(FP), CX
MOVL W_55+220(FP), DX
XORL DX, CX
SHRL $0x1d, CX
ANDL $0x00000001, CX
NEGL CX
ORL $0xffff5fff, CX
ANDL CX, AX
f34:
// mask &= ((((W[47] ^ W[49]) & (1 << 6)) - (1 << 6)) | ^(DV_I_49_2_bit | DV_I_51_2_bit))
MOVL W_47+188(FP), CX
MOVL W_49+196(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
SUBL $0x00000040, CX
ORL $0xffffbbff, CX
ANDL CX, AX
// mask &= ((((W[48] ^ (W[47] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_47_2_bit | DV_II_51_2_bit))
MOVL W_48+192(FP), CX
MOVL W_47+188(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
SUBL $0x00000002, CX
ORL $0xfbffffbf, CX
ANDL CX, AX
// mask &= ((((W[46] ^ W[48]) & (1 << 6)) - (1 << 6)) | ^(DV_I_48_2_bit | DV_I_50_2_bit))
MOVL W_46+184(FP), CX
MOVL W_48+192(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
SUBL $0x00000040, CX
ORL $0xffffeeff, CX
ANDL CX, AX
// mask &= ((((W[47] ^ (W[46] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_46_2_bit | DV_II_50_2_bit))
MOVL W_47+188(FP), CX
MOVL W_46+184(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
SUBL $0x00000002, CX
ORL $0xfeffffef, CX
ANDL CX, AX
// mask &= ((0 - ((W[44] ^ (W[45] >> 5)) & (1 << 1))) | ^(DV_I_51_2_bit | DV_II_49_2_bit))
MOVL W_44+176(FP), CX
MOVL W_45+180(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xffbfbfff, CX
ANDL CX, AX
// mask &= ((((W[43] ^ W[45]) & (1 << 6)) - (1 << 6)) | ^(DV_I_47_2_bit | DV_I_49_2_bit))
MOVL W_43+172(FP), CX
MOVL W_45+180(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
SUBL $0x00000040, CX
ORL $0xfffffbbf, CX
ANDL CX, AX
// mask &= (((((W[42] ^ W[44]) >> 6) & 1) - 1) | ^(DV_I_46_2_bit | DV_I_48_2_bit))
MOVL W_42+168(FP), CX
MOVL W_44+176(FP), DX
XORL DX, CX
SHRL $0x06, CX
ANDL $0x00000001, CX
SUBL $0x00000001, CX
ORL $0xfffffeef, CX
ANDL CX, AX
// mask &= ((((W[43] ^ (W[42] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_II_46_2_bit | DV_II_51_2_bit))
MOVL W_43+172(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
SUBL $0x00000002, CX
ORL $0xfbfbffff, CX
ANDL CX, AX
// mask &= ((((W[42] ^ (W[41] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_51_2_bit | DV_II_50_2_bit))
MOVL W_42+168(FP), CX
MOVL W_41+164(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
SUBL $0x00000002, CX
ORL $0xfeffbfff, CX
ANDL CX, AX
// mask &= ((((W[41] ^ (W[40] >> 5)) & (1 << 1)) - (1 << 1)) | ^(DV_I_50_2_bit | DV_II_49_2_bit))
MOVL W_41+164(FP), CX
MOVL W_40+160(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
SUBL $0x00000002, CX
ORL $0xffbfefff, CX
ANDL CX, AX
// if (mask & (DV_I_52_0_bit | DV_II_51_0_bit)) != 0 {
// mask &= ((((W[39] ^ (W[43] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_52_0_bit | DV_II_51_0_bit))
// }
TESTL $0x02008000, AX
JE f35
MOVL W_39+156(FP), CX
MOVL W_43+172(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xfdff7fff, CX
ANDL CX, AX
f35:
// if (mask & (DV_I_51_0_bit | DV_II_50_0_bit)) != 0 {
// mask &= ((((W[38] ^ (W[42] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_51_0_bit | DV_II_50_0_bit))
// }
TESTL $0x00802000, AX
JE f36
MOVL W_38+152(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xff7fdfff, CX
ANDL CX, AX
f36:
// if (mask & (DV_I_48_2_bit | DV_I_51_2_bit)) != 0 {
// mask &= ((0 - ((W[37] ^ (W[38] >> 5)) & (1 << 1))) | ^(DV_I_48_2_bit | DV_I_51_2_bit))
// }
TESTL $0x00004100, AX
JE f37
MOVL W_37+148(FP), CX
MOVL W_38+152(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xffffbeff, CX
ANDL CX, AX
f37:
// if (mask & (DV_I_50_0_bit | DV_II_49_0_bit)) != 0 {
// mask &= ((((W[37] ^ (W[41] >> 25)) & (1 << 4)) - (1 << 4)) | ^(DV_I_50_0_bit | DV_II_49_0_bit))
// }
TESTL $0x00200800, AX
JE f38
MOVL W_37+148(FP), CX
MOVL W_41+164(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
SUBL $0x00000010, CX
ORL $0xffdff7ff, CX
ANDL CX, AX
f38:
// if (mask & (DV_II_52_0_bit | DV_II_54_0_bit)) != 0 {
// mask &= ((0 - ((W[36] ^ W[38]) & (1 << 4))) | ^(DV_II_52_0_bit | DV_II_54_0_bit))
// }
TESTL $0x28000000, AX
JE f39
MOVL W_36+144(FP), CX
MOVL W_38+152(FP), DX
XORL DX, CX
ANDL $0x00000010, CX
NEGL CX
ORL $0xd7ffffff, CX
ANDL CX, AX
f39:
// mask &= ((0 - ((W[35] ^ (W[36] >> 5)) & (1 << 1))) | ^(DV_I_46_2_bit | DV_I_49_2_bit))
MOVL W_35+140(FP), CX
MOVL W_36+144(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
ORL $0xfffffbef, CX
ANDL CX, AX
// if (mask & (DV_I_51_0_bit | DV_II_47_0_bit)) != 0 {
// mask &= ((((W[35] ^ (W[39] >> 25)) & (1 << 3)) - (1 << 3)) | ^(DV_I_51_0_bit | DV_II_47_0_bit))
// }
TESTL $0x00082000, AX
JE f40
MOVL W_35+140(FP), CX
MOVL W_39+156(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
SUBL $0x00000008, CX
ORL $0xfff7dfff, CX
ANDL CX, AX
f40:
// if mask != 0
TESTL $0x00000000, AX
JNE end
// if (mask & DV_I_43_0_bit) != 0 {
// if not((W[61]^(W[62]>>5))&(1<<1)) != 0 ||
// not(not((W[59]^(W[63]>>25))&(1<<5))) != 0 ||
// not((W[58]^(W[63]>>30))&(1<<0)) != 0 {
// mask &= ^DV_I_43_0_bit
// }
// }
BTL $0x00, AX
JNC f41_skip
MOVL W_61+244(FP), CX
MOVL W_62+248(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
CMPL CX, $0x00000000
JE f41_in
MOVL W_59+236(FP), CX
MOVL W_63+252(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000020, CX
CMPL CX, $0x00000000
JNE f41_in
MOVL W_58+232(FP), CX
MOVL W_63+252(FP), DX
SHRL $0x1e, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
CMPL CX, $0x00000000
JE f41_in
JMP f41_skip
f41_in:
ANDL $0xfffffffe, AX
f41_skip:
// if (mask & DV_I_44_0_bit) != 0 {
// if not((W[62]^(W[63]>>5))&(1<<1)) != 0 ||
// not(not((W[60]^(W[64]>>25))&(1<<5))) != 0 ||
// not((W[59]^(W[64]>>30))&(1<<0)) != 0 {
// mask &= ^DV_I_44_0_bit
// }
// }
BTL $0x01, AX
JNC f42_skip
MOVL W_62+248(FP), CX
MOVL W_63+252(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
CMPL CX, $0x00000000
JE f42_in
MOVL W_60+240(FP), CX
MOVL W_64+256(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000020, CX
CMPL CX, $0x00000000
JNE f42_in
MOVL W_59+236(FP), CX
MOVL W_64+256(FP), DX
SHRL $0x1e, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
CMPL CX, $0x00000000
JE f42_in
JMP f42_skip
f42_in:
ANDL $0xfffffffd, AX
f42_skip:
// if (mask & DV_I_46_2_bit) != 0 {
// mask &= ((^((W[40] ^ W[42]) >> 2)) | ^DV_I_46_2_bit)
// }
BTL $0x04, AX
JNC f43
MOVL W_40+160(FP), CX
MOVL W_42+168(FP), DX
XORL DX, CX
SHRL $0x02, CX
NOTL CX
ORL $0xffffffef, CX
ANDL CX, AX
f43:
// if (mask & DV_I_47_2_bit) != 0 {
// if not((W[62]^(W[63]>>5))&(1<<2)) != 0 ||
// not(not((W[41]^W[43])&(1<<6))) != 0 {
// mask &= ^DV_I_47_2_bit
// }
// }
BTL $0x06, AX
JNC f44_skip
MOVL W_62+248(FP), CX
MOVL W_63+252(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000004, CX
NEGL CX
CMPL CX, $0x00000000
JE f44_in
MOVL W_41+164(FP), CX
MOVL W_43+172(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f44_in
JMP f44_skip
f44_in:
ANDL $0xffffffbf, AX
f44_skip:
// if (mask & DV_I_48_2_bit) != 0 {
// if not((W[63]^(W[64]>>5))&(1<<2)) != 0 ||
// not(not((W[48]^(W[49]<<5))&(1<<6))) != 0 {
// mask &= ^DV_I_48_2_bit
// }
// }
BTL $0x08, AX
JNC f45_skip
MOVL W_63+252(FP), CX
MOVL W_64+256(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000004, CX
NEGL CX
CMPL CX, $0x00000000
JE f45_in
MOVL W_48+192(FP), CX
MOVL W_49+196(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f45_in
JMP f45_skip
f45_in:
ANDL $0xfffffeff, AX
f45_skip:
// if (mask & DV_I_49_2_bit) != 0 {
// if not(not((W[49]^(W[50]<<5))&(1<<6))) != 0 ||
// not((W[42]^W[50])&(1<<1)) != 0 ||
// not(not((W[39]^(W[40]<<5))&(1<<6))) != 0 ||
// not((W[38]^W[40])&(1<<1)) != 0 {
// mask &= ^DV_I_49_2_bit
// }
// }
BTL $0x0a, AX
JNC f46_skip
MOVL W_49+196(FP), CX
MOVL W_50+200(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f46_in
MOVL W_42+168(FP), CX
MOVL W_50+200(FP), DX
XORL DX, CX
ANDL $0x00000002, CX
CMPL CX, $0x00000000
JE f46_in
MOVL W_39+156(FP), CX
MOVL W_40+160(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f46_in
MOVL W_38+152(FP), CX
MOVL W_40+160(FP), DX
XORL DX, CX
ANDL $0x00000002, CX
CMPL CX, $0x00000000
JE f46_in
JMP f46_skip
f46_in:
ANDL $0xfffffbff, AX
f46_skip:
// if (mask & DV_I_50_0_bit) != 0 {
// mask &= (((W[36] ^ W[37]) << 7) | ^DV_I_50_0_bit)
// }
BTL $0x0b, AX
JNC f47
MOVL W_36+144(FP), CX
MOVL W_37+148(FP), DX
XORL DX, CX
SHLL $0x07, CX
ORL $0xfffff7ff, CX
ANDL CX, AX
f47:
// if (mask & DV_I_50_2_bit) != 0 {
// mask &= (((W[43] ^ W[51]) << 11) | ^DV_I_50_2_bit)
// }
BTL $0x0c, AX
JNC f48
MOVL W_43+172(FP), CX
MOVL W_51+204(FP), DX
XORL DX, CX
SHLL $0x0b, CX
ORL $0xffffefff, CX
ANDL CX, AX
f48:
// if (mask & DV_I_51_0_bit) != 0 {
// mask &= (((W[37] ^ W[38]) << 9) | ^DV_I_51_0_bit)
// }
BTL $0x0d, AX
JNC f49
MOVL W_37+148(FP), CX
MOVL W_38+152(FP), DX
XORL DX, CX
SHLL $0x09, CX
ORL $0xffffdfff, CX
ANDL CX, AX
f49:
// if (mask & DV_I_51_2_bit) != 0 {
// if not(not((W[51]^(W[52]<<5))&(1<<6))) != 0 ||
// not(not((W[49]^W[51])&(1<<6))) != 0 ||
// not(not((W[37]^(W[37]>>5))&(1<<1))) != 0 ||
// not(not((W[35]^(W[39]>>25))&(1<<5))) != 0 {
// mask &= ^DV_I_51_2_bit
// }
// }
BTL $0x0e, AX
JNC f50_skip
MOVL W_51+204(FP), CX
MOVL W_52+208(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f50_in
MOVL W_49+196(FP), CX
MOVL W_51+204(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f50_in
MOVL W_37+148(FP), CX
MOVL W_37+148(FP), DX
SHRL $0x05, DX
XORL DX, CX
ANDL $0x00000002, CX
CMPL CX, $0x00000000
JNE f50_in
MOVL W_35+140(FP), CX
MOVL W_39+156(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000020, CX
CMPL CX, $0x00000000
JNE f50_in
JMP f50_skip
f50_in:
ANDL $0xffffbfff, AX
f50_skip:
// if (mask & DV_I_52_0_bit) != 0 {
// mask &= (((W[38] ^ W[39]) << 11) | ^DV_I_52_0_bit)
// }
BTL $0x0f, AX
JNC f51
MOVL W_38+152(FP), CX
MOVL W_39+156(FP), DX
XORL DX, CX
SHLL $0x0b, CX
ORL $0xffff7fff, CX
ANDL CX, AX
f51:
// if (mask & DV_II_46_2_bit) != 0 {
// mask &= (((W[47] ^ W[51]) << 17) | ^DV_II_46_2_bit)
// }
TESTL $0x00040000, AX
BTL $0x12, AX
JNC f52
MOVL W_47+188(FP), CX
MOVL W_51+204(FP), DX
XORL DX, CX
SHLL $0x11, CX
ORL $0xfffbffff, CX
ANDL CX, AX
f52:
// if (mask & DV_II_48_0_bit) != 0 {
// if not(not((W[36]^(W[40]>>25))&(1<<3))) != 0 ||
// not((W[35]^(W[40]<<2))&(1<<30)) != 0 {
// mask &= ^DV_II_48_0_bit
// }
// }
BTL $0x14, AX
JNC f53_skip
MOVL W_36+144(FP), CX
MOVL W_40+160(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f53_in
MOVL W_35+140(FP), CX
MOVL W_40+160(FP), DX
SHLL $0x02, DX
XORL DX, CX
ANDL $0x40000000, CX
CMPL CX, $0x00000000
JNE f53_in
JMP f53_skip
f53_in:
ANDL $0xffefffff, AX
f53_skip:
// if (mask & DV_II_49_0_bit) != 0 {
// if not(not((W[37]^(W[41]>>25))&(1<<3))) != 0 ||
// not((W[36]^(W[41]<<2))&(1<<30)) != 0 {
// mask &= ^DV_II_49_0_bit
// }
// }
BTL $0x15, AX
JNC f54_skip
MOVL W_37+148(FP), CX
MOVL W_41+164(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f54_in
MOVL W_36+144(FP), CX
MOVL W_41+164(FP), DX
SHLL $0x02, DX
XORL DX, CX
ANDL $0x40000000, CX
CMPL CX, $0x00000000
JNE f54_in
JMP f54_skip
f54_in:
ANDL $0xffdfffff, AX
f54_skip:
// if (mask & DV_II_49_2_bit) != 0 {
// if not(not((W[53]^(W[54]<<5))&(1<<6))) != 0 ||
// not(not((W[51]^W[53])&(1<<6))) != 0 ||
// not((W[50]^W[54])&(1<<1)) != 0 ||
// not(not((W[45]^(W[46]<<5))&(1<<6))) != 0 ||
// not(not((W[37]^(W[41]>>25))&(1<<5))) != 0 ||
// not((W[36]^(W[41]>>30))&(1<<0)) != 0 {
// mask &= ^DV_II_49_2_bit
// }
// }
BTL $0x16, AX
JNC f55_skip
MOVL W_53+212(FP), CX
MOVL W_54+216(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f55_in
MOVL W_51+204(FP), CX
MOVL W_53+212(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f55_in
MOVL W_50+200(FP), CX
MOVL W_54+216(FP), DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
CMPL CX, $0x00000000
JE f55_in
MOVL W_45+180(FP), CX
MOVL W_46+184(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f55_in
MOVL W_37+148(FP), CX
MOVL W_41+164(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000020, CX
CMPL CX, $0x00000000
JNE f55_in
MOVL W_36+144(FP), CX
MOVL W_41+164(FP), DX
SHRL $0x1e, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
CMPL CX, $0x00000000
JE f55_in
JMP f55_skip
f55_in:
ANDL $0xffbfffff, AX
f55_skip:
// if (mask & DV_II_50_0_bit) != 0 {
// if not((W[55]^W[58])&(1<<29)) != 0 ||
// not(not((W[38]^(W[42]>>25))&(1<<3))) != 0 ||
// not((W[37]^(W[42]<<2))&(1<<30)) != 0 {
// mask &= ^DV_II_50_0_bit
// }
// }
BTL $0x17, AX
JNC f56_skip
MOVL W_55+220(FP), CX
MOVL W_58+232(FP), DX
XORL DX, CX
ANDL $0x20000000, CX
NEGL CX
CMPL CX, $0x00000000
JE f56_in
MOVL W_38+152(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f56_in
MOVL W_37+148(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x02, DX
XORL DX, CX
ANDL $0x40000000, CX
NEGL CX
CMPL CX, $0x00000000
JE f56_in
JMP f56_skip
f56_in:
ANDL $0xff7fffff, AX
f56_skip:
// if (mask & DV_II_50_2_bit) != 0 {
// if not(not((W[54]^(W[55]<<5))&(1<<6))) != 0 ||
// not(not((W[52]^W[54])&(1<<6))) != 0 ||
// not((W[51]^W[55])&(1<<1)) != 0 ||
// not((W[45]^W[47])&(1<<1)) != 0 ||
// not(not((W[38]^(W[42]>>25))&(1<<5))) != 0 ||
// not((W[37]^(W[42]>>30))&(1<<0)) != 0 {
// mask &= ^DV_II_50_2_bit
// }
// }
BTL $0x18, AX
JNC f57_skip
MOVL W_54+216(FP), CX
MOVL W_55+220(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f57_in
MOVL W_52+208(FP), CX
MOVL W_54+216(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f57_in
MOVL W_51+204(FP), CX
MOVL W_55+220(FP), DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
CMPL CX, $0x00000000
JE f57_in
MOVL W_45+180(FP), CX
MOVL W_47+188(FP), DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
CMPL CX, $0x00000000
JE f57_in
MOVL W_38+152(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000020, CX
CMPL CX, $0x00000000
JNE f57_in
MOVL W_37+148(FP), CX
MOVL W_42+168(FP), DX
SHRL $0x1e, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
CMPL CX, $0x00000000
JE f57_in
JMP f57_skip
f57_in:
ANDL $0xfeffffff, AX
f57_skip:
// if (mask & DV_II_51_0_bit) != 0 {
// if not(not((W[39]^(W[43]>>25))&(1<<3))) != 0 ||
// not((W[38]^(W[43]<<2))&(1<<30)) != 0 {
// mask &= ^DV_II_51_0_bit
// }
// }
BTL $0x19, AX
JNC f58_skip
MOVL W_39+156(FP), CX
MOVL W_43+172(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f58_in
MOVL W_38+152(FP), CX
MOVL W_43+172(FP), DX
SHLL $0x02, DX
XORL DX, CX
ANDL $0x40000000, CX
NEGL CX
CMPL CX, $0x00000000
JE f58_in
JMP f58_skip
f58_in:
ANDL $0xfdffffff, AX
f58_skip:
// if (mask & DV_II_51_2_bit) != 0 {
// if not(not((W[55]^(W[56]<<5))&(1<<6))) != 0 ||
// not(not((W[53]^W[55])&(1<<6))) != 0 ||
// not((W[52]^W[56])&(1<<1)) != 0 ||
// not((W[46]^W[48])&(1<<1)) != 0 ||
// not(not((W[39]^(W[43]>>25))&(1<<5))) != 0 ||
// not((W[38]^(W[43]>>30))&(1<<0)) != 0 {
// mask &= ^DV_II_51_2_bit
// }
// }
BTL $0x1a, AX
JNC f59_skip
MOVL W_55+220(FP), CX
MOVL W_56+224(FP), DX
SHLL $0x05, DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f59_in
MOVL W_53+212(FP), CX
MOVL W_55+220(FP), DX
XORL DX, CX
ANDL $0x00000040, CX
CMPL CX, $0x00000000
JNE f59_in
MOVL W_52+208(FP), CX
MOVL W_56+224(FP), DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
CMPL CX, $0x00000000
JE f59_in
MOVL W_46+184(FP), CX
MOVL W_48+192(FP), DX
XORL DX, CX
ANDL $0x00000002, CX
NEGL CX
CMPL CX, $0x00000000
JE f59_in
MOVL W_39+156(FP), CX
MOVL W_43+172(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000020, CX
CMPL CX, $0x00000000
JNE f59_in
MOVL W_38+152(FP), CX
MOVL W_43+172(FP), DX
SHRL $0x1e, DX
XORL DX, CX
ANDL $0x00000001, CX
NEGL CX
CMPL CX, $0x00000000
JE f59_in
JMP f59_skip
f59_in:
ANDL $0xfbffffff, AX
f59_skip:
// if (mask & DV_II_52_0_bit) != 0 {
// if not(not((W[59]^W[60])&(1<<29))) != 0 ||
// not(not((W[40]^(W[44]>>25))&(1<<3))) != 0 ||
// not(not((W[40]^(W[44]>>25))&(1<<4))) != 0 ||
// not((W[39]^(W[44]<<2))&(1<<30)) != 0 {
// mask &= ^DV_II_52_0_bit
// }
// }
BTL $0x1b, AX
JNC f60_skip
MOVL W_59+236(FP), CX
MOVL W_60+240(FP), DX
XORL DX, CX
ANDL $0x20000000, CX
CMPL CX, $0x00000000
JNE f60_in
MOVL W_40+160(FP), CX
MOVL W_44+176(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f60_in
MOVL W_40+160(FP), CX
MOVL W_44+176(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f60_in
MOVL W_39+156(FP), CX
MOVL W_44+176(FP), DX
SHLL $0x02, DX
XORL DX, CX
ANDL $0x40000000, CX
NEGL CX
CMPL CX, $0x00000000
JE f60_in
JMP f60_skip
f60_in:
ANDL $0xf7ffffff, AX
f60_skip:
// if (mask & DV_II_53_0_bit) != 0 {
// if not((W[58]^W[61])&(1<<29)) != 0 ||
// not(not((W[57]^(W[61]>>25))&(1<<4))) != 0 ||
// not(not((W[41]^(W[45]>>25))&(1<<3))) != 0 ||
// not(not((W[41]^(W[45]>>25))&(1<<4))) != 0 {
// mask &= ^DV_II_53_0_bit
// }
// }
BTL $0x1c, AX
JNC f61_skip
MOVL W_58+232(FP), CX
MOVL W_61+244(FP), DX
XORL DX, CX
ANDL $0x20000000, CX
NEGL CX
CMPL CX, $0x00000000
JE f61_in
MOVL W_57+228(FP), CX
MOVL W_61+244(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f61_in
MOVL W_41+164(FP), CX
MOVL W_45+180(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f61_in
MOVL W_41+164(FP), CX
MOVL W_45+180(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f61_in
JMP f61_skip
f61_in:
ANDL $0xefffffff, AX
f61_skip:
// if (mask & DV_II_54_0_bit) != 0 {
// if not(not((W[58]^(W[62]>>25))&(1<<4))) != 0 ||
// not(not((W[42]^(W[46]>>25))&(1<<3))) != 0 ||
// not(not((W[42]^(W[46]>>25))&(1<<4))) != 0 {
// mask &= ^DV_II_54_0_bit
// }
// }
BTL $0x1d, AX
JNC f62_skip
MOVL W_58+232(FP), CX
MOVL W_62+248(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f62_in
MOVL W_42+168(FP), CX
MOVL W_46+184(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f62_in
MOVL W_42+168(FP), CX
MOVL W_46+184(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f62_in
JMP f62_skip
f62_in:
ANDL $0xdfffffff, AX
f62_skip:
// if (mask & DV_II_55_0_bit) != 0 {
// if not(not((W[59]^(W[63]>>25))&(1<<4))) != 0 ||
// not(not((W[57]^(W[59]>>25))&(1<<4))) != 0 ||
// not(not((W[43]^(W[47]>>25))&(1<<3))) != 0 ||
// not(not((W[43]^(W[47]>>25))&(1<<4))) != 0 {
// mask &= ^DV_II_55_0_bit
// }
// }
BTL $0x1e, AX
JNC f63_skip
MOVL W_59+236(FP), CX
MOVL W_63+252(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f63_in
MOVL W_57+228(FP), CX
MOVL W_59+236(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f63_in
MOVL W_43+172(FP), CX
MOVL W_47+188(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f63_in
MOVL W_43+172(FP), CX
MOVL W_47+188(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f63_in
JMP f63_skip
f63_in:
ANDL $0xbfffffff, AX
f63_skip:
// if (mask & DV_II_56_0_bit) != 0 {
// if not(not((W[60]^(W[64]>>25))&(1<<4))) != 0 ||
// not(not((W[44]^(W[48]>>25))&(1<<3))) != 0 ||
// not(not((W[44]^(W[48]>>25))&(1<<4))) != 0 {
// mask &= ^DV_II_56_0_bit
// }
// }
BTL $0x1f, AX
JNC f64_skip
MOVL W_60+240(FP), CX
MOVL W_64+256(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f64_in
MOVL W_44+176(FP), CX
MOVL W_48+192(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000008, CX
CMPL CX, $0x00000000
JNE f64_in
MOVL W_44+176(FP), CX
MOVL W_48+192(FP), DX
SHRL $0x19, DX
XORL DX, CX
ANDL $0x00000010, CX
CMPL CX, $0x00000000
JNE f64_in
JMP f64_skip
f64_in:
ANDL $0x7fffffff, AX
f64_skip:
end:
MOVL AX, ret+320(FP)
RET
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